tree 76d47f1d8ed1f249a81682447f900cbf076b134b
parent 447f5777aae39600af421b230d6ab22a18b96e84
author Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> 1669765506 -0800
committer Martin L Roth <gaumless@gmail.com> 1671073884 +0000

soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode

Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.

BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings

Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>