gm45: Declare BIOS memory as RAM.
So it's in line with other boards and those addresses are cached for faster
access.
Change-Id: I7794d75ef1e3ceea6b2a4acba01e4af5d1f005f5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6689
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 42561e4..7a4b038 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -34,14 +34,12 @@
#include "gm45.h"
#include "arch/acpi.h"
-/* Reserve everything between A segment and 1MB:
+/* Reserve segments A and B:
*
* 0xa0000 - 0xbffff: legacy VGA
- * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
- * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
*/
static const int legacy_hole_base_k = 0xa0000 / 1024;
-static const int legacy_hole_size_k = 384;
+static const int legacy_hole_size_k = 128;
static int decode_pcie_bar(u32 *const base, u32 *const len)
{