dram/ddr3: Use the same naming convention as DDR4
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 7109e46..d97ab2a 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -252,14 +252,14 @@
dimm->dimm_num = d_num;
dimm->bank_locator = ch * 2;
memcpy(dimm->serial,
- &pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM],
- SPD_DIMM_SERIAL_LEN);
+ &pei_data->spd_data[index][SPD_DDR3_SERIAL_NUM],
+ SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number,
- &pei_data->spd_data[index][SPD_DIMM_PART_NUM],
- SPD_DIMM_PART_LEN);
+ &pei_data->spd_data[index][SPD_DDR3_PART_NUM],
+ SPD_DDR3_PART_LEN);
dimm->mod_id =
- (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) |
- (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff);
+ (pei_data->spd_data[index][SPD_DDR3_MOD_ID2] << 8) |
+ (pei_data->spd_data[index][SPD_DDR3_MOD_ID1] & 0xff);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;