| commit | 8adaffcbed6372970f34b85177bd42bb508d03e2 | [log] [tgz] |
|---|---|---|
| author | Subrata Banik <subrata.banik@intel.com> | Sat Aug 10 21:43:12 2019 +0530 |
| committer | Subrata Banik <subrata.banik@intel.com> | Mon Aug 12 05:24:19 2019 +0000 |
| tree | 2d21ff7d3347fc043f572c9d4dd091f3c59601db | |
| parent | e2e1f12265e8591431280c28070b452d449a0131 [diff] [blame] |
soc/intel/common: Fix typo mistake in cache_as_ram.S Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: V Sowmya <v.sowmya@intel.com>
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index b1648e8..d5f5081 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -365,7 +365,7 @@ jnz find_llc_subleaf /* - * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE * for 4/8/16 way of LLC */ shr $22, %ebx