commit 8ab989e31561cea0c6af5d5e242dd2be97bc73b4
author Elyes HAOUAS <ehaouas@noos.fr> Sat Jul 30 17:46:17 2016 +0200
committer Martin Roth <martinroth@google.com> Sun Aug 14 19:06:25 2016 +0200
tree 31bc3a2175762b179d2fc093c34f62c18b15b9ee
parent 589ef9de8faa2db11a7ce2769fc1d9396a82886b

src/mainboard: Capitalize ROM, RAM, CPU and APIC

Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/supermicro/h8dmr_fam10/resourcemap.c

diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
index b71448a..b35d3e5 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
@@ -268,7 +268,7 @@
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 		// WARD CHANGED
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,