commit 8ab989e31561cea0c6af5d5e242dd2be97bc73b4
author Elyes HAOUAS <ehaouas@noos.fr> Sat Jul 30 17:46:17 2016 +0200
committer Martin Roth <martinroth@google.com> Sun Aug 14 19:06:25 2016 +0200
tree 31bc3a2175762b179d2fc093c34f62c18b15b9ee
parent 589ef9de8faa2db11a7ce2769fc1d9396a82886b

src/mainboard: Capitalize ROM, RAM, CPU and APIC

Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/amd/pistachio/fadt.c

diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/amd/pistachio/fadt.c
+++ b/src/mainboard/amd/pistachio/fadt.c
@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */