haswell: Move some MRC settings to devicetree
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index 9bdb8dd..119d007 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -27,8 +27,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index 0573b6b..deb6ec9 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -25,8 +25,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index f4c9e85..304f3cf 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -9,6 +9,10 @@
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
+ register "dq_pins_interleaved" = "true"
+
+ register "usb_xhci_on_resume" = "true"
+
device cpu_cluster 0 on
chip cpu/intel/haswell
device lapic 0 on end
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 8410d04..ee14630 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -48,10 +48,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
- pei_data->dq_pins_interleaved = 1;
- pei_data->usb_xhci_on_resume = 1;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: VP8 */
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 3d98d74..e22a41e 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -14,6 +14,10 @@
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
+ register "ec_present" = "true"
+
+ register "usb_xhci_on_resume" = "true"
+
device cpu_cluster 0 on
chip cpu/intel/haswell
device lapic 0 on end
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index 47bcb47..7f08a58 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -49,8 +49,5 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
- pei_data->usb_xhci_on_resume = 1;
-
variant_romstage_entry(pei_data);
}
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 5641775..1927517 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -51,8 +51,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb
index e18f72b..58f0ca8 100644
--- a/src/mainboard/lenovo/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/t440p/devicetree.cb
@@ -11,6 +11,7 @@
register "gpu_panel_power_down_delay" = "500"
register "gpu_panel_power_up_delay" = "2000"
register "gpu_pch_backlight_pwm_hz" = "220"
+ register "ec_present" = "true"
device cpu_cluster 0x0 on
chip cpu/intel/haswell
register "c1_acpower" = "1"
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index 8c2c5b6..3e5cc0d 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -48,8 +48,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 1;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 036a89c..c9f1027 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -27,8 +27,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_INTERNAL },
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index 593144d..28c0828 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -32,6 +32,12 @@
bool gpu_ddi_e_connected;
+ bool ec_present;
+
+ bool dq_pins_interleaved;
+
+ bool usb_xhci_on_resume;
+
struct i915_gpu_controller_info gfx;
};
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 7016fd9..dfadad2 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -10,6 +10,7 @@
#include <commonlib/helpers.h>
#include <romstage_handoff.h>
#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/chip.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -40,6 +41,8 @@
{
const struct device *gbe = pcidev_on_root(0x19, 0);
+ const struct northbridge_intel_haswell_config *cfg = config_of_soc();
+
int wake_from_s3;
struct pei_data pei_data = {
@@ -56,9 +59,12 @@
.temp_mmio_base = 0xfed08000,
.system_type = get_pch_platform_type(),
.tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .ec_present = cfg->ec_present,
.gbe_enable = gbe && gbe->enabled,
.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
+ .dq_pins_interleaved = cfg->dq_pins_interleaved,
.max_ddr3_freq = 1600,
+ .usb_xhci_on_resume = cfg->usb_xhci_on_resume,
};
mainboard_fill_pei_data(&pei_data);