soc/amd/cezanne: add console UART support
Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index afee1ef..f7f2d68 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -25,6 +25,7 @@
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
+ select SOC_AMD_COMMON_BLOCK_UART
config CHIPSET_DEVICETREE
string
@@ -106,4 +107,10 @@
int
default 64
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
+ hex
+ default 0xfedc9000 if UART_FOR_CONSOLE = 0
+ default 0xfedca000 if UART_FOR_CONSOLE = 1
+
endif # SOC_AMD_CEZANNE
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 5ffe06f..6a0229c 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -11,17 +11,21 @@
bootblock-y += early_fch.c
bootblock-y += gpio.c
bootblock-y += reset.c
+bootblock-y += uart.c
verstage_x86-y += gpio.c
verstage_x86-y += reset.c
+verstage_x86-y += uart.c
romstage-y += gpio.c
romstage-y += reset.c
romstage-y += romstage.c
+romstage-y += uart.c
ramstage-y += chip.c
ramstage-y += gpio.c
ramstage-y += reset.c
+ramstage-y += uart.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 6616d07..b6681e3 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -4,6 +4,7 @@
#include <amdblocks/smbus.h>
#include <console/console.h>
#include <soc/southbridge.h>
+#include <soc/uart.h>
/* Before console init */
void fch_pre_init(void)
@@ -12,6 +13,15 @@
fch_smbus_init();
fch_enable_cf9_io();
fch_enable_legacy_io();
+
+ /*
+ * On reset Range_0 defaults to enabled. We want to start with a clean
+ * slate to not have things unexpectedly enabled.
+ */
+ clear_uart_legacy_config();
+
+ if (CONFIG(AMD_SOC_CONSOLE_UART))
+ set_uart_config(CONFIG_UART_FOR_CONSOLE);
}
/* After console init */
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index b377ee3..20f7037 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -3,6 +3,14 @@
#ifndef AMD_CEZANNE_IOMAP_H
#define AMD_CEZANNE_IOMAP_H
+/* FCH AL2AHB Registers */
+#define ALINK_AHB_ADDRESS 0xfedc0000
+
+#define APU_DMAC0_BASE 0xfedc7000
+#define APU_DMAC1_BASE 0xfedc8000
+#define APU_UART0_BASE 0xfedc9000
+#define APU_UART1_BASE 0xfedca000
+
/* MMIO Ranges */
#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index ec4f3a7..7fb61b6 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -10,6 +10,8 @@
#define TOGGLE_ALL_PWR_GOOD (1 << 1)
#define PM_ACPI_SMI_CMD 0x6a
+#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
+
/* IO 0xf0 NCP Error */
#define NCP_WARM_BOOT (1 << 7) /* Write-once */
diff --git a/src/soc/amd/cezanne/include/soc/uart.h b/src/soc/amd/cezanne/include/soc/uart.h
new file mode 100644
index 0000000..9b99cd4
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/uart.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_PICASSO_UART_H
+#define AMD_PICASSO_UART_H
+
+#include <types.h>
+
+void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */
+void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */
+
+#endif /* AMD_PICASSO_UART_H */
diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c
new file mode 100644
index 0000000..02a6d22
--- /dev/null
+++ b/src/soc/amd/cezanne/uart.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/gpio_banks.h>
+#include <amdblocks/uart.h>
+#include <commonlib/helpers.h>
+#include <device/mmio.h>
+#include <soc/gpio.h>
+#include <soc/southbridge.h>
+#include <soc/uart.h>
+#include <types.h>
+
+static const struct _uart_info {
+ uintptr_t base;
+ struct soc_amd_gpio mux[2];
+} uart_info[] = {
+ [0] = { APU_UART0_BASE, {
+ PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
+ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
+ } },
+ [1] = { APU_UART1_BASE, {
+ PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
+ PAD_NF(GPIO_142, UART1_RXD, PULL_NONE),
+ } },
+};
+
+uintptr_t get_uart_base(unsigned int idx)
+{
+ if (idx >= ARRAY_SIZE(uart_info))
+ return 0;
+
+ return uart_info[idx].base;
+}
+
+void clear_uart_legacy_config(void)
+{
+ write16((void *)FCH_LEGACY_UART_DECODE, 0);
+}
+
+void set_uart_config(unsigned int idx)
+{
+ if (idx >= ARRAY_SIZE(uart_info))
+ return;
+
+ program_gpios(uart_info[idx].mux, 2);
+}