diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 6c5329a..f926887 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -13,6 +13,7 @@
 
 config SOC_AMD_COMMON_BLOCK_NONCAR
 	bool
+	select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT
 	help
 	  From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
 	  more, since the RAM initialization is already done by the PSP when
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
index 3204667..f8ca357 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
@@ -2,6 +2,7 @@
 ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y)
 
 bootblock-y += bootblock.c
+bootblock-y += cpu.c
 bootblock-y += early_cache.c
 bootblock-y += pre_c.S
 bootblock-y += write_resume_eip.c
diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c
index eec593c..eefd62f 100644
--- a/src/soc/amd/common/block/cpu/noncar/cpu.c
+++ b/src/soc/amd/common/block/cpu/noncar/cpu.c
@@ -35,7 +35,8 @@
 	wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
 }
 
-static uint32_t get_sme_reserved_address_bits(void)
+/* Number of most significant physical address bits reserved for secure memory encryption */
+unsigned int get_reserved_phys_addr_bits(void)
 {
 	if (rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE)
 		return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) &
@@ -44,8 +45,3 @@
 	else
 		return 0;
 }
-
-uint32_t get_usable_physical_address_bits(void)
-{
-	return cpu_phys_address_size() - get_sme_reserved_address_bits();
-}
diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c
index 4004726..ae00885 100644
--- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c
+++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c
@@ -65,6 +65,11 @@
 	uintptr_t tseg_base;
 	size_t tseg_size;
 
+	/* For the TSEG masks all physical address bits including the ones reserved for memory
+	   encryption need to be taken into account. TODO: Find out why this is the case */
+	const unsigned int total_physical_address_bits =
+		cpu_phys_address_size() + get_reserved_phys_addr_bits();
+
 	smm_region(&tseg_base, &tseg_size);
 
 	msr_t msr;
@@ -73,7 +78,7 @@
 
 	msr.lo = ~(tseg_size - 1);
 	msr.lo |= SMM_TSEG_WB;
-	msr.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
+	msr.hi = (1 << (total_physical_address_bits - 32)) - 1;
 	wrmsr(SMM_MASK_MSR, msr);
 
 	uintptr_t smbase = smm_get_cpu_smbase(cpu_index());
diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c
index ca685b2..01fad99 100644
--- a/src/soc/amd/common/block/data_fabric/domain.c
+++ b/src/soc/amd/common/block/data_fabric/domain.c
@@ -1,13 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpigen.h>
-#include <amdblocks/cpu.h>
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/root_complex.h>
 #include <arch/ioapic.h>
 #include <arch/vga.h>
 #include <console/console.h>
 #include <cpu/amd/mtrr.h>
+#include <cpu/cpu.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <types.h>
@@ -90,7 +90,7 @@
 
 	/* The last 12GB of the usable address space are reserved and can't be used for MMIO */
 	const resource_t reserved_upper_mmio_base =
-		(1ULL << get_usable_physical_address_bits()) - DF_RESERVED_TOP_12GB_MMIO_SIZE;
+		(1ULL << cpu_phys_address_size()) - DF_RESERVED_TOP_12GB_MMIO_SIZE;
 
 	for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
 		ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
index 10dd23f..4aa225b 100644
--- a/src/soc/amd/common/block/include/amdblocks/cpu.h
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -12,7 +12,6 @@
 int get_cpu_count(void);
 unsigned int get_threads_per_core(void);
 void set_cstate_io_addr(void);
-uint32_t get_usable_physical_address_bits(void);
 void write_resume_eip(void);
 
 union pstate_msr; /* proper definition is in soc/msr.h */