tree 32b36ab0ffab7151ec00a1841702f938f51f2250
parent 0a635ab1e875bc96c8c00221659f6e75b4e1db14
author Mario Scheithauer <mario.scheithauer@siemens.com> 1651150103 +0200
committer Felix Held <felix-coreboot@felixheld.de> 1652792193 +0000

mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge

On this mainboard there are legacy PCI devices connected behind a
PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This
patch disables the unused PCI clock outputs on the XIO2001 bridge.

Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>