nb/intel/sandybridge: Use cached CPUID
Now that we have it, we might as well pass it around.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 9eb60c7..41d683b 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -168,15 +168,14 @@
static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
{
- u32 addr, cpu, stretch;
+ u32 addr, stretch;
stretch = ctrl->ref_card_offset[channel];
/*
* ODT stretch:
* Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel.
*/
- cpu = cpu_get_cpuid();
- if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
+ if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) {
if (stretch == 2)
stretch = 3;
@@ -2992,10 +2991,8 @@
}
}
-void set_wmm_behavior(void)
+void set_wmm_behavior(const u32 cpu)
{
- u32 cpu = cpu_get_cpuid();
-
if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) {
MCHBAR32(SC_WDBWM) = 0x141d1519;
} else {
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 0cbac8a..0ff9265 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -181,7 +181,7 @@
void write_controller_mr(ramctr_timing *ctrl);
int channel_test(ramctr_timing *ctrl);
void set_scrambling_seed(ramctr_timing *ctrl);
-void set_wmm_behavior(void);
+void set_wmm_behavior(const u32 cpu);
void prepare_training(ramctr_timing *ctrl);
void set_read_write_timings(ramctr_timing *ctrl);
void set_normal_operation(ramctr_timing *ctrl);
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 06d2382..a714e53 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -609,7 +609,7 @@
MCHBAR32(SCHED_CBIT) = 0x10100005;
/* Set up watermarks and starvation counter */
- set_wmm_behavior();
+ set_wmm_behavior(ctrl->cpu);
/* Clear IO reset bit */
MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5);
diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c
index c554c3a..a823d50 100644
--- a/src/northbridge/intel/sandybridge/raminit_sandy.c
+++ b/src/northbridge/intel/sandybridge/raminit_sandy.c
@@ -433,7 +433,7 @@
MCHBAR32(SCHED_CBIT) = 0x10100005;
/* Set up watermarks and starvation counter */
- set_wmm_behavior();
+ set_wmm_behavior(ctrl->cpu);
/* Clear IO reset bit */
MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5);