soc/intel: Use config_of()
Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 33c5455..b2b2d3c 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -108,11 +108,11 @@
reg_script_run_on_dev(dev, init_script);
if (is_first_port(dev)) {
- struct soc_intel_baytrail_config *config = dev->chip_info;
+ struct soc_intel_baytrail_config *config = config_of(dev);
uint32_t reg = pci_read_config32(dev, RPPGEN);
reg |= SRDLCGEN | SRDBCGEN;
- if (config && config->clkreq_enable)
+ if (config->clkreq_enable)
reg |= LCLKREQEN | BBCLKREQEN;
pci_write_config32(dev, RPPGEN, reg);
@@ -208,13 +208,13 @@
static void byt_pcie_enable(struct device *dev)
{
if (is_first_port(dev)) {
- struct soc_intel_baytrail_config *config = dev->chip_info;
+ struct soc_intel_baytrail_config *config = config_of(dev);
uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL);
pll_en_off = !!(reg & PLL_OFF_EN);
strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
- if (config && config->pcie_wake_enable)
+ if (config->pcie_wake_enable)
southcluster_smm_save_param(
SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
}