soc/amd/mendocino: Update XHCI GPE to use constant
The GPE number used for XHCI has now been defined in AMD's common code
in CB:67936. Change over existing code to use this new definition.
BUG=b:186792595
TEST=Ran on skyrim device and verified XHCI GPE setting.
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I3bfc2256ea2ca851afe88f2cdb419f39eee76fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69916
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/mendocino/xhci.c b/src/soc/amd/mendocino/xhci.c
index fdd0118..720cc76 100644
--- a/src/soc/amd/mendocino/xhci.c
+++ b/src/soc/amd/mendocino/xhci.c
@@ -4,6 +4,7 @@
#include <amdblocks/gpio.h>
#include <amdblocks/smi.h>
+#include <amdblocks/xhci.h>
#include <bootstate.h>
#include <device/device.h>
#include <device/pci_ids.h>
@@ -14,19 +15,19 @@
static const struct sci_source xhci_sci_sources[] = {
{
.scimap = SMITYPE_XHC0_PME,
- .gpe = GEVENT_31,
+ .gpe = XHCI_GEVENT,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
},
{
.scimap = SMITYPE_XHC1_PME,
- .gpe = GEVENT_31,
+ .gpe = XHCI_GEVENT,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
},
{
.scimap = SMITYPE_XHC2_PME,
- .gpe = GEVENT_31,
+ .gpe = XHCI_GEVENT,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
}