soc/mediatek/mt8183: Fix DDR phy config number
Some typos are fixed to make DVFS switch work.
BUG=b:142358843
BRANCH=kukui
TEST=emerge-kukui coreboot
Change-Id: I064d4a2c46187ac5780352da742bd56e82c22c14
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c
index b077767..26ff71a 100644
--- a/src/soc/mediatek/mt8183/dramc_init_setting.c
+++ b/src/soc/mediatek/mt8183/dramc_init_setting.c
@@ -873,7 +873,7 @@
clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
(0x2 << 4) | (0x0 << 7) | (0x0 << 13));
clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20);
- clrbits_le32(&ch[0].phy.b[0].dq[7], (0x1 << 7) | (0x1 << 13));
+ clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13));
for (size_t r = 0; r < 2; r++) {
int value = ((r == 0) ? 0x1a : 0x26);
@@ -931,7 +931,7 @@
clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
(0x1 << 4) | (0x1 << 7) | (0x1 << 13));
clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20);
- clrsetbits_le32(&ch[0].phy.b[0].dq[7],
+ clrsetbits_le32(&ch[0].phy.b[1].dq[7],
(0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13));
for (size_t r = 0; r < 2; r++) {