| commit | 88af0f38eb19f956e8df2b62254c10c7603a9a33 | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Sun Jun 03 12:37:54 2018 +0200 |
| committer | Arthur Heymans <arthur@aheymans.xyz> | Tue Jun 05 07:59:22 2018 +0000 |
| tree | 97fdbf21a0dca3c0f6c5473e9bf92c0b954df33a | |
| parent | 02b13fd8cdfbfcb4858ec0e6f66688b96950198e [diff] |
cpu/intel/haswell: Switch to POSTCAR_STAGE Tested on Google Peppy (Acer C720). Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26793 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 5c8caea..5e6956e 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig
@@ -21,6 +21,8 @@ select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select POSTCAR_STAGE + select POSTCAR_CONSOLE if NORTHBRIDGE_INTEL_HASWELL
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index c6d6b2e..055c2a8 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -36,4 +36,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc +postcar-y += ram_calc.c + endif