mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
This patch adds initial romstage code and spd data for LP5 memory
parts for MTL-RVP. This also configures memory based on the board id.
Memory - x32 LPDDR5
Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B
Board ID -
0b0000 - Empty spd hex file
0b0001 - DDR5 (Empty spd hex file)
0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B)
BUG=b:224325352
TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: I15b352eb246aed23da273e56490c7094eae9d176
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 9d8982d..945aa2e 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -3,6 +3,7 @@
select BOARD_ROMSIZE_KB_32768
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
+ select HAVE_SPD_IN_CBFS
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_METEORLAKE
@@ -63,6 +64,9 @@
string
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+config DIMM_SPD_SIZE
+ default 512
+
choice
prompt "ON BOARD EC"
default MTL_INTEL_EC if BOARD_INTEL_MTLRVP_P
diff --git a/src/mainboard/intel/mtlrvp/Makefile.inc b/src/mainboard/intel/mtlrvp/Makefile.inc
index 795b9ae..4dc41af 100644
--- a/src/mainboard/intel/mtlrvp/Makefile.inc
+++ b/src/mainboard/intel/mtlrvp/Makefile.inc
@@ -17,6 +17,7 @@
subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
subdirs-y += variants/baseboard/$(BASEBOARD_DIR)/memory
subdirs-y += variants/$(VARIANT_DIR)
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
diff --git a/src/mainboard/intel/mtlrvp/romstage.c b/src/mainboard/intel/mtlrvp/romstage.c
index ecfaee0..b5bb777 100644
--- a/src/mainboard/intel/mtlrvp/romstage.c
+++ b/src/mainboard/intel/mtlrvp/romstage.c
@@ -5,12 +5,32 @@
#include <ec/intel/board_id.h>
#include <soc/romstage.h>
+#define SPD_ID_MASK 0x7
+
+static size_t get_spd_index(void)
+{
+ uint8_t board_id = get_rvp_board_id();
+ size_t spd_index;
+
+ printk(BIOS_INFO, "board id is 0x%x\n", board_id);
+
+ spd_index = board_id & SPD_ID_MASK;
+
+ printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index);
+ return spd_index;
+}
+
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct mb_cfg *mem_config = variant_memory_params();
int board_id = get_rvp_board_id();
const bool half_populated = false;
+ const struct mem_spd memory_down_spd_info = {
+ .topo = MEM_TOPO_MEMORY_DOWN,
+ .cbfs_index = get_spd_index(),
+ };
+
const struct mem_spd dimm_module_spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
@@ -37,6 +57,10 @@
case MTLP_DDR5_RVP:
memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated);
break;
+ case MTLP_LP5_T3_RVP:
+ case MTLP_LP5_T4_RVP:
+ memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated);
+ break;
default:
die("Unknown board id = 0x%x\n", board_id);
break;
diff --git a/src/mainboard/intel/mtlrvp/spd/Makefile.inc b/src/mainboard/intel/mtlrvp/spd/Makefile.inc
new file mode 100644
index 0000000..be4d98b
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/spd/Makefile.inc
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+ifneq ($(SPD_SOURCES),)
+LIB_SPD_DEPS := $(SPD_SOURCES)
+endif
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/Makefile.inc b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/Makefile.inc
index 566f5cc..f4faac3 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/Makefile.inc
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/Makefile.inc
@@ -1,3 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-or-later
romstage-y += memory.c
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-empty.hex # ID = 0(0b0000)
+SPD_SOURCES += spd/lp5/set-0/spd-empty.hex # ID = 1(0b0001)
+SPD_SOURCES += spd/lp5/set-0/spd-4.hex # ID = 2(0b0010) Parts = MT62F2G32D8DR-031 WT:B
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/dram_id.generated.txt b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/dram_id.generated.txt
new file mode 100644
index 0000000..9d3992e
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/ src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/mem_parts_used.txt
+
+DRAM Part Name ID to assign
+MT62F2G32D8DR-031 WT:B 2 (0010)
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/mem_parts_used.txt b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/mem_parts_used.txt
new file mode 100644
index 0000000..e2ba4e1
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+
+# Part Name
+MT62F2G32D8DR-031 WT:B,2
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c
index d4a53c8..c17e99f 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c
@@ -5,6 +5,68 @@
#include <ec/intel/board_id.h>
#include <soc/romstage.h>
+static const struct mb_cfg lp5_mem_config = {
+ .type = MEM_TYPE_LP5X,
+
+ /* DQ byte map as per doc #573387 */
+ .lpx_dq_map = {
+ .ddr0 = {
+ .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, },
+ .dq1 = { 12, 13, 14, 15, 11, 9, 10, 8 },
+ },
+ .ddr1 = {
+ .dq0 = { 3, 0, 1, 2, 5, 7, 6, 4, },
+ .dq1 = { 13, 10, 12, 15, 9, 11, 8, 14 },
+ },
+ .ddr2 = {
+ .dq0 = { 2, 1, 3, 0, 7, 5, 6, 4, },
+ .dq1 = { 12, 8, 13, 15, 11, 10, 9, 14 },
+ },
+ .ddr3 = {
+ .dq0 = { 4, 3, 0, 1, 5, 2, 6, 7, },
+ .dq1 = { 8, 15, 12, 14, 10, 13, 9, 11 },
+ },
+ .ddr4 = {
+ .dq0 = { 1, 3, 2, 6, 7, 5, 4, 0, },
+ .dq1 = { 14, 13, 12, 15, 11, 10, 8, 9 },
+ },
+ .ddr5 = {
+ .dq0 = { 0, 7, 3, 6, 2, 5, 1, 4, },
+ .dq1 = { 9, 10, 11, 8, 13, 14, 15, 12 },
+ },
+ .ddr6 = {
+ .dq0 = { 3, 0, 2, 1, 6, 5, 4, 7, },
+ .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9 },
+ },
+ .ddr7 = {
+ .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5, },
+ .dq1 = { 14, 12, 13, 15, 9, 10, 11, 8 },
+ },
+ },
+
+ /* DQS CPU<>DRAM map as per doc #573387 */
+ .lpx_dqs_map = {
+ .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+ },
+
+ .ect = false, /* Early Command Training */
+
+ .LpDdrDqDqsReTraining = 1,
+
+ .UserBd = BOARD_TYPE_ULT_ULX,
+
+ .lp5x_config = {
+ .ccc_config = 0,
+ },
+};
+
static const struct mb_cfg ddr5_mem_config = {
.type = MEM_TYPE_DDR5,
@@ -31,6 +93,9 @@
switch (board_id) {
case MTLP_DDR5_RVP:
return &ddr5_mem_config;
+ case MTLP_LP5_T3_RVP:
+ case MTLP_LP5_T4_RVP:
+ return &lp5_mem_config;
default:
die("Unknown board id = 0x%x\n", board_id);
break;