src: Use tabs for indentation
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c
index 75e1820..66ff9d2 100644
--- a/src/device/hypertransport.c
+++ b/src/device/hypertransport.c
@@ -265,7 +265,7 @@
min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- /*
+ /*
* Let's record the device of last HT device, so we can set the unitid
* to CONFIG_HT_CHAIN_END_UNITID_BASE.
*/
diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c
index aa262d7..4918630 100644
--- a/src/drivers/i2c/at24rf08c/at24rf08c.c
+++ b/src/drivers/i2c/at24rf08c/at24rf08c.c
@@ -28,7 +28,7 @@
if (!dev->enabled)
return;
- /* Ensure that EEPROM/RFID chip is not accessible through RFID.
+ /* Ensure that EEPROM/RFID chip is not accessible through RFID.
Need to do it only on 5c. */
if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c)
return;
diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c
index d0d006f..0209bb2 100644
--- a/src/drivers/i2c/at24rf08c/lenovo_serials.c
+++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c
@@ -39,7 +39,7 @@
int t = -1;
int j;
- /* After a register write AT24RF08C (which we issued in init function)
+ /* After a register write AT24RF08C (which we issued in init function)
sometimes stops responding. Retry several times in case of failure.
*/
for (j = 0; j < 100; j++) {
diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c
index e7c3c71..5caa1b3 100644
--- a/src/drivers/intel/gma/int15.c
+++ b/src/drivers/intel/gma/int15.c
@@ -103,7 +103,7 @@
}
break;
- default:
+ default:
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
break;
}
diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h
index 048985d..a6ec487 100644
--- a/src/drivers/intel/gma/intel_bios.h
+++ b/src/drivers/intel/gma/intel_bios.h
@@ -108,14 +108,14 @@
#define BDB_SKIP 254 /* VBIOS private block, ignore */
struct bdb_general_features {
- /* bits 1 */
+ /* bits 1 */
u8 panel_fitting:2;
u8 flexaim:1;
u8 msg_enable:1;
u8 clear_screen:3;
u8 color_flip:1;
- /* bits 2 */
+ /* bits 2 */
u8 download_ext_vbt:1;
u8 enable_ssc:1;
u8 ssc_freq:1;
@@ -125,17 +125,17 @@
u8 display_clock_mode:1;
u8 rsvd8:1; /* finish byte */
- /* bits 3 */
+ /* bits 3 */
u8 disable_smooth_vision:1;
u8 single_dvi:1;
u8 rsvd9:1;
u8 fdi_rx_polarity_inverted:1;
u8 rsvd10:4; /* finish byte */
- /* bits 4 */
+ /* bits 4 */
u8 legacy_monitor_detect;
- /* bits 5 */
+ /* bits 5 */
u8 int_crt_support:1;
u8 int_tv_support:1;
u8 int_efp_support:1;
@@ -603,7 +603,7 @@
#define SWF14_PM_APM_12 (0x2 << 16)
#define SWF14_PM_APM_11 (0x1 << 16)
#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
- /* if GR18 indicates a display switch */
+ /* if GR18 indicates a display switch */
#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
#define SWF14_DS_PIPEB_TV2_EN (1<<13)
@@ -620,9 +620,9 @@
#define SWF14_DS_PIPEA_EFP_EN (1<<2)
#define SWF14_DS_PIPEA_TV_EN (1<<1)
#define SWF14_DS_PIPEA_CRT_EN (1<<0)
- /* if GR18 indicates a panel fitting request */
+ /* if GR18 indicates a panel fitting request */
#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
- /* if GR18 indicates an APM change request */
+ /* if GR18 indicates an APM change request */
#define SWF14_APM_HIBERNATE 0x4
#define SWF14_APM_SUSPEND 0x3
#define SWF14_APM_STANDBY 0x1
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index cdce6e2..cf0f6d8 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -265,7 +265,7 @@
val = pci_read_config16(dev, PMCS_DR);
if (val & PME_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0);
- }
+ }
}
static struct pci_operations pci_ops = {
diff --git a/src/drivers/vpd/lib_vpd.h b/src/drivers/vpd/lib_vpd.h
index 7a7566b..156d279 100644
--- a/src/drivers/vpd/lib_vpd.h
+++ b/src/drivers/vpd/lib_vpd.h
@@ -34,8 +34,8 @@
/* Callback for decodeVpdString to invoke. */
typedef int VpdDecodeCallback(const uint8_t *key, int32_t key_len,
- const uint8_t *value, int32_t value_len,
- void *arg);
+ const uint8_t *value, int32_t value_len,
+ void *arg);
/* Container data types */
struct StringPair {
@@ -153,53 +153,53 @@
void initContainer(struct PairContainer *container);
struct StringPair *findString(struct PairContainer *container,
- const uint8_t *key,
- struct StringPair ***prev_next);
+ const uint8_t *key,
+ struct StringPair ***prev_next);
/* If key is already existed in container, its value will be replaced.
* If not existed, creates new entry in container.
*/
void setString(struct PairContainer *container,
- const uint8_t *key,
- const uint8_t *value,
- const int pad_len);
+ const uint8_t *key,
+ const uint8_t *value,
+ const int pad_len);
/* merge all entries in src into dst. If key is duplicate, overwrite it.
*/
void mergeContainer(struct PairContainer *dst,
- const struct PairContainer *src);
+ const struct PairContainer *src);
/* subtract src from dst.
*/
int subtractContainer(struct PairContainer *dst,
- const struct PairContainer *src);
+ const struct PairContainer *src);
/* Given a container, encode its all entries into the buffer.
*/
int encodeContainer(const struct PairContainer *container,
- const int max_buf_len,
- uint8_t *buf,
- int *generated);
+ const int max_buf_len,
+ uint8_t *buf,
+ int *generated);
/* Given a VPD blob, decode its entries and push into container.
*/
int decodeToContainer(struct PairContainer *container,
- const int32_t max_len,
- const uint8_t *input_buf,
- int32_t *consumed);
+ const int32_t max_len,
+ const uint8_t *input_buf,
+ int32_t *consumed);
/* Set filter for exporting functions.
* If filter is NULL, resets the filter so that everything can be exported.
*/
int setContainerFilter(struct PairContainer *container,
- const uint8_t *filter);
+ const uint8_t *filter);
/*
* Remove a key.
* Returns VPD_OK if deleted successfully. Otherwise, VPD_FAIL.
*/
int deleteKey(struct PairContainer *container,
- const uint8_t *key);
+ const uint8_t *key);
/*
* Returns number of pairs in container.
@@ -216,10 +216,10 @@
* generated.
*/
int exportContainer(const int export_type,
- const struct PairContainer *container,
- const int max_buf_len,
- uint8_t *buf,
- int *generated);
+ const struct PairContainer *container,
+ const int max_buf_len,
+ uint8_t *buf,
+ int *generated);
void destroyContainer(struct PairContainer *container);
diff --git a/src/ec/roda/it8518/acpi/ec.asl b/src/ec/roda/it8518/acpi/ec.asl
index e0639e2..94b00ce 100644
--- a/src/ec/roda/it8518/acpi/ec.asl
+++ b/src/ec/roda/it8518/acpi/ec.asl
@@ -146,12 +146,12 @@
{
Store ("-----> EC: _Q43", Debug)
- Store (BRIG, Local0)
- Increment (Local0)
- If (LGreater (Local0, 0xAA)) {
+ Store (BRIG, Local0)
+ Increment (Local0)
+ If (LGreater (Local0, 0xAA)) {
Store (0xAA, Local0)
- }
- Store (Local0, BRIG)
+ }
+ Store (Local0, BRIG)
\_SB.PCI0.GFX0.INCB ()
@@ -162,13 +162,13 @@
{
Store ("-----> EC: _Q44", Debug)
- Store (BRIG, Local0)
- Decrement (Local0)
- If (LLess (Local0, 0xA0))
- {
+ Store (BRIG, Local0)
+ Decrement (Local0)
+ If (LLess (Local0, 0xA0))
+ {
Store (0xA0, Local0)
- }
- Store (Local0, BRIG)
+ }
+ Store (Local0, BRIG)
\_SB.PCI0.GFX0.DECB ()
diff --git a/src/ec/smsc/mec1308/acpi/ec.asl b/src/ec/smsc/mec1308/acpi/ec.asl
index 39a27e1..a7a0739 100644
--- a/src/ec/smsc/mec1308/acpi/ec.asl
+++ b/src/ec/smsc/mec1308/acpi/ec.asl
@@ -193,7 +193,7 @@
} Else {
Return (Zero)
}
- }
+ }
Method (_ON) {
If (FCOS) {
Store (One, FSL4)
diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
index e0195c6..9d249e2 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -26,7 +26,7 @@
#include <include/device/pci_def.h>
u32 Get_NB32(u32 dev, u32 reg)
{
- return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg);
+ return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg);
}
#endif
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 8704d39..64131d8 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -43,7 +43,7 @@
static void set_db(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
{
- struct db_limit limit;
+ struct db_limit limit;
switch (s->selected_timings.mem_clk) {
default:
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index b90e2d4..b9dac56 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -209,7 +209,7 @@
static void vx900_lpc_set_resources(struct device *dev)
{
struct resource *mmio, *spi;
- u32 reg;
+ u32 reg;
mmio = find_resource(dev, VX900_MMCONFIG_MBAR);
if (mmio) {
diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c
index 23f6471..91c591e 100644
--- a/src/soc/imgtec/pistachio/bootblock.c
+++ b/src/soc/imgtec/pistachio/bootblock.c
@@ -58,5 +58,5 @@
C0_ENTRYLO_COHERENCY_WB));
assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB));
assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size,
- C0_ENTRYLO_COHERENCY_UC));
+ C0_ENTRYLO_COHERENCY_UC));
}
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index bf93ef4..9226ac3 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -174,7 +174,7 @@
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
- cfg = dev->chip_info;
+ cfg = dev->chip_info;
if(cfg->lpss_s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 4ea8971..ba10e35 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -573,7 +573,7 @@
void __weak mainboard_devtree_update(struct device *dev)
{
- /* Override dev tree settings per board */
+ /* Override dev tree settings per board */
}
void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c
index a46b188..6a71f1ee 100644
--- a/src/soc/intel/apollolake/nhlt.c
+++ b/src/soc/intel/apollolake/nhlt.c
@@ -260,7 +260,7 @@
int nhlt_soc_add_rt5682(struct nhlt *nhlt, int hwlink)
{
- /* Virtual bus id of SSP links are the hardware port ids proper. */
- return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5682_descriptors,
- ARRAY_SIZE(rt5682_descriptors));
+ /* Virtual bus id of SSP links are the hardware port ids proper. */
+ return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5682_descriptors,
+ ARRAY_SIZE(rt5682_descriptors));
}
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 5da5104..451993d 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -170,7 +170,7 @@
}
static void setup_gpio_route(const struct soc_gpio_map *sus,
- const struct soc_gpio_map *core)
+ const struct soc_gpio_map *core)
{
uint32_t route_reg = 0;
int i;
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 30e6d1d..51c3ea0 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -52,7 +52,7 @@
}
static void print_num_status_bits(int num_bits, uint32_t status,
- const char *bit_names[])
+ const char *bit_names[])
{
int i;
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 027e0d8..07b8010 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -97,8 +97,8 @@
}
/* Entry from cache-as-ram.inc. */
-void *asmlinkage romstage_main(unsigned long bist,
- uint32_t tsc_low, uint32_t tsc_hi)
+void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
+ uint32_t tsc_hi)
{
struct romstage_params rp = {
.bist = bist,
diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c
index 0f47173..300556a 100644
--- a/src/soc/intel/cannonlake/cbmem.c
+++ b/src/soc/intel/cannonlake/cbmem.c
@@ -17,6 +17,6 @@
void *cbmem_top(void)
{
- /* not implemented yet */
+ /* not implemented yet */
return (void *) NULL;
}
diff --git a/src/soc/intel/cannonlake/nhlt.c b/src/soc/intel/cannonlake/nhlt.c
index ff1b446..ca31d39 100644
--- a/src/soc/intel/cannonlake/nhlt.c
+++ b/src/soc/intel/cannonlake/nhlt.c
@@ -231,7 +231,7 @@
.did = NHLT_DID_SSP,
.formats = max98373_capture_formats,
.num_formats = ARRAY_SIZE(max98373_capture_formats),
- },
+ },
};
int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels)
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 45ee940..225914c 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -155,8 +155,8 @@
if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
dpr_size = sa_get_dpr_size();
- /* Get SoC reserve memory size as per user selection */
- reserved_mmio_size = soc_reserved_mmio_size();
+ /* Get SoC reserve memory size as per user selection */
+ reserved_mmio_size = soc_reserved_mmio_size();
top_of_ram = (uintptr_t)cbmem_top();
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index 72cf158..72ba517 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -186,7 +186,7 @@
}
static void setup_gpio_route(const struct soc_gpio_map *sus,
- const struct soc_gpio_map *core)
+ const struct soc_gpio_map *core)
{
uint32_t route_reg = 0;
int i;
@@ -319,7 +319,7 @@
* pad value: PAD_VAL_HIGH / PAD_VAL_LOW
*/
static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
- uint32_t pconf0, uint32_t pad_val)
+ uint32_t pconf0, uint32_t pad_val)
{
uint32_t reg;
uint32_t *pad_addr;
diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl
index f99b7c3..9798798 100644
--- a/src/soc/intel/skylake/acpi/dptf/thermal.asl
+++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl
@@ -266,34 +266,34 @@
#ifdef DPTF_ENABLE_FAN_CONTROL
#ifdef DPTF_TSR1_ACTIVE_AC0
- Method (_AC0)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
- }
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+ }
#endif
#ifdef DPTF_TSR1_ACTIVE_AC1
- Method (_AC1)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
- }
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+ }
#endif
#ifdef DPTF_TSR1_ACTIVE_AC2
- Method (_AC2)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
- }
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+ }
#endif
#ifdef DPTF_TSR1_ACTIVE_AC3
- Method (_AC3)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
- }
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+ }
#endif
#ifdef DPTF_TSR1_ACTIVE_AC4
- Method (_AC4)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
- }
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+ }
#endif
#endif
}
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index 29367de..a23d78a 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -195,8 +195,8 @@
Store (3, ^UPSW)
/* Enable d3hot and SS link trunk clock gating */
- Store(One, ^D3HE)
- Store(One, ^STGE)
+ Store(One, ^D3HE)
+ Store(One, ^STGE)
/* Now put device in D3 */
Store (3, Local0)
diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c
index beb4558..0e3a413 100644
--- a/src/soc/intel/skylake/nhlt/max98373.c
+++ b/src/soc/intel/skylake/nhlt/max98373.c
@@ -75,7 +75,7 @@
.did = NHLT_DID_SSP,
.formats = max98373_capture_formats,
.num_formats = ARRAY_SIZE(max98373_capture_formats),
- },
+ },
};
int nhlt_soc_add_max98373(struct nhlt *nhlt, int hwlink)
diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
index 4babd54..b582657 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
@@ -39,7 +39,7 @@
const struct mt8173_sdram_params *sdram_params)
{
/* judge ranks from EMI_CONA[17] (cha) and EMI_CONA[16] (chb) */
- return (sdram_params->emi_set.cona & (1 << (17 - channel))) ? 1 : 0;
+ return (sdram_params->emi_set.cona & (1 << (17 - channel))) ? 1 : 0;
}
static void mem_pll_pre_init(u32 channel)
diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
index 8ed82b1..7a25bfe 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
@@ -343,7 +343,7 @@
gw_ret[i] = dqs_gw_test(channel);
/* judge test result */
if (gw_ret[i] != 0)
- return opt_coarse_val[i];
+ return opt_coarse_val[i];
}
/* abnormal test result, set to default coarse tune value */
@@ -747,7 +747,7 @@
}
/* Default dle value is set when test error (error recovery).
- * Others, adjusted dle calibration value is set normally.
+ * Others, adjusted dle calibration value is set normally.
*/
set_dle_factor(channel, best_step);
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c
index 4f6ba32..ecea693 100644
--- a/src/soc/mediatek/mt8173/mt6391.c
+++ b/src/soc/mediatek/mt8173/mt6391.c
@@ -86,7 +86,7 @@
mt6391_write(PMIC_RG_ANALDO_CON6, vsel - 2, PMIC_RG_VCAMA_VOSEL_MASK,
PMIC_RG_VCAMA_VOSEL_SHIFT);
mt6391_write(PMIC_RG_ANALDO_CON2, 1, PMIC_RG_VCAMA_EN_MASK,
- PMIC_RG_VCAMA_EN_SHIFT);
+ PMIC_RG_VCAMA_EN_SHIFT);
}
void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index 7d3e0bf..4db7808 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -212,7 +212,7 @@
struct tegra_i2c_regs *regs;
if (bus >= g_num_i2c_buses) {
- printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__,
+ printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__,
bus);
return;
}
diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h
index d9ab67b..7e930d1 100644
--- a/src/soc/nvidia/tegra124/chip.h
+++ b/src/soc/nvidia/tegra124/chip.h
@@ -75,7 +75,7 @@
int hpd_unplug_min_us;
int hpd_plug_min_us;
- int hpd_irq_min_us;
+ int hpd_irq_min_us;
int href_to_sync;
int hsync_width;
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c
index febb420..c90e392 100644
--- a/src/soc/nvidia/tegra124/display.c
+++ b/src/soc/nvidia/tegra124/display.c
@@ -40,26 +40,26 @@
int dump = 0;
unsigned long READL(void *p)
{
- unsigned long value;
+ unsigned long value;
/*
* In case of hard hung on readl(p), we can set dump > 1 to print out
* the address accessed.
*/
- if (dump > 1)
+ if (dump > 1)
printk(BIOS_SPEW, "readl %p\n", p);
- value = read32(p);
- if (dump)
+ value = read32(p);
+ if (dump)
printk(BIOS_SPEW, "readl %p %08lx\n", p, value);
- return value;
+ return value;
}
void WRITEL(unsigned long value, void *p)
{
- if (dump)
+ if (dump)
printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
- write32(p, value);
+ write32(p, value);
}
/* return in 1000ths of a Hertz */
diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c
index a9b8d7d..7fae4e9 100644
--- a/src/soc/nvidia/tegra124/dp.c
+++ b/src/soc/nvidia/tegra124/dp.c
@@ -1362,10 +1362,10 @@
struct tegra_dc *dc = config->dc_data;
struct tegra_dc_dp_data *dp = &dp_data;
- // set up links among config, dc, dp and sor
- dp->dc = dc;
- dc->out = dp;
- dp->sor.dc = dc;
+ // set up links among config, dc, dp and sor
+ dp->dc = dc;
+ dc->out = dp;
+ dp->sor.dc = dc;
dp->sor.power_is_up = 0;
dp->sor.base = (void *)TEGRA_ARM_SOR;
@@ -1427,7 +1427,7 @@
if (tegra_dc_dp_init_max_link_cfg(config, dp, &dp->link_cfg)) {
printk(BIOS_ERR, "dp: failed to init link configuration\n");
goto error_enable;
- }
+ }
tegra_dc_sor_enable_dp(&dp->sor);
diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c
index b892c60..1000346 100644
--- a/src/soc/nvidia/tegra210/dc.c
+++ b/src/soc/nvidia/tegra210/dc.c
@@ -25,26 +25,26 @@
int dump = 0;
unsigned long READL(void *p)
{
- unsigned long value;
+ unsigned long value;
/*
* In case of hard hung on readl(p), we can set dump > 1 to print out
* the address accessed.
*/
- if (dump > 1)
+ if (dump > 1)
printk(BIOS_SPEW, "readl %p\n", p);
- value = read32(p);
- if (dump)
+ value = read32(p);
+ if (dump)
printk(BIOS_SPEW, "readl %p %08lx\n", p, value);
- return value;
+ return value;
}
void WRITEL(unsigned long value, void *p)
{
- if (dump)
+ if (dump)
printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
- write32(p, value);
+ write32(p, value);
}
/* return in 1000ths of a Hertz */
@@ -76,7 +76,7 @@
}
int update_display_mode(struct display_controller *disp_ctrl,
- struct soc_nvidia_tegra210_config *config)
+ struct soc_nvidia_tegra210_config *config)
{
print_mode(config);
@@ -124,7 +124,7 @@
}
void update_display_shift_clock_divider(struct display_controller *disp_ctrl,
- u32 shift_clock_div)
+ u32 shift_clock_div)
{
WRITEL((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
(shift_clock_div & 0xff) << SHIFT_CLK_DIVIDER_SHIFT,
diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c
index 532ffc3..205bc1e 100644
--- a/src/soc/nvidia/tegra210/dsi.c
+++ b/src/soc/nvidia/tegra210/dsi.c
@@ -886,12 +886,12 @@
/*
* Set default value. Will be taken from attached device once detected
*/
- dsi->flags = 0;
- dsi->format = MIPI_DSI_FMT_RGB888;
- dsi->lanes = 4;
+ dsi->flags = 0;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->lanes = 4;
/* get tegra_mipi_device */
- dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index);
+ dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index);
/* calibrate */
err = tegra_dsi_pad_calibrate(dsi);
diff --git a/src/soc/nvidia/tegra210/romstage_asm.S b/src/soc/nvidia/tegra210/romstage_asm.S
index 9bceadb..110149b 100644
--- a/src/soc/nvidia/tegra210/romstage_asm.S
+++ b/src/soc/nvidia/tegra210/romstage_asm.S
@@ -16,7 +16,7 @@
#include <arch/asm.h>
#include "stack.S"
- .section ".text", "ax", %progbits
+ .section ".text", "ax", %progbits
ENTRY(main)
stack_init stack_top=_estack stack_bottom=_stack seed=0 func=romstage
diff --git a/src/soc/nvidia/tegra210/stack.S b/src/soc/nvidia/tegra210/stack.S
index acab70c..416cdb3 100644
--- a/src/soc/nvidia/tegra210/stack.S
+++ b/src/soc/nvidia/tegra210/stack.S
@@ -21,7 +21,7 @@
* @func : Function to call after initializing stack
*/
.macro stack_init stack_top, stack_bottom, seed, func
- /* Check if stack seeding is required */
+ /* Check if stack seeding is required */
mov r0, #\seed
cmp r0, #1
bne call_func
diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c
index 4498b31..d47b9c5 100644
--- a/src/soc/qualcomm/ipq40xx/spi.c
+++ b/src/soc/qualcomm/ipq40xx/spi.c
@@ -657,7 +657,7 @@
|| ((bus == BLSP1_SPI) && (cs > 0))) {
printk(BIOS_ERR,
"SPI error: unsupported bus %d (Supported busses 0, 1 and 2) "
- "or chipselect\n", bus);
+ "or chipselect\n", bus);
return -1;
}
diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c
index 35a3283..15e9e6f 100644
--- a/src/soc/qualcomm/ipq806x/gpio.c
+++ b/src/soc/qualcomm/ipq806x/gpio.c
@@ -63,17 +63,17 @@
unsigned pull, unsigned drvstr,
unsigned enable)
{
- unsigned val = 0;
+ unsigned val = 0;
if (gpio_not_valid(gpio))
return;
- val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT;
- val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT;
- val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT;
- val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT;
+ val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT;
+ val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT;
+ val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT;
+ val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT;
- write32(GPIO_CONFIG_ADDR(gpio), val);
+ write32(GPIO_CONFIG_ADDR(gpio), val);
}
/*******************************************************
@@ -93,8 +93,8 @@
unsigned *pull, unsigned *drvstr,
unsigned *enable)
{
- unsigned val;
- void *addr = GPIO_CONFIG_ADDR(gpio);
+ unsigned val;
+ void *addr = GPIO_CONFIG_ADDR(gpio);
if (gpio_not_valid(gpio))
return;
diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c
index ea4778b..295ef39 100644
--- a/src/soc/samsung/exynos5420/clock_init.c
+++ b/src/soc/samsung/exynos5420/clock_init.c
@@ -41,7 +41,7 @@
write32(&exynos_clock->ipll_lock, IPLL_LOCK_VAL);
write32(&exynos_clock->spll_lock, SPLL_LOCK_VAL);
write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL);
- write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL);
+ write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL);
setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK);
@@ -138,7 +138,7 @@
while ((read32(&exynos_clock->spll_con0) & PLL_LOCKED) == 0)
;
- /* We use RPLL as the source for FIMD video stream clock */
+ /* We use RPLL as the source for FIMD video stream clock */
write32(&exynos_clock->rpll_con1, RPLL_CON1_VAL);
write32(&exynos_clock->rpll_con2, RPLL_CON2_VAL);
/* computed by gabe from first principles; u-boot is probably
diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c
index a7adf93..aa850bc 100644
--- a/src/soc/samsung/exynos5420/fimd.c
+++ b/src/soc/samsung/exynos5420/fimd.c
@@ -304,16 +304,16 @@
static void exynos5_set_system_display(void)
{
- unsigned int cfg = 0;
+ unsigned int cfg = 0;
- /*
- * system register path set
- * 0: MIE/MDNIE
- * 1: FIMD Bypass
- */
- cfg = lreadl(&exynos_sysreg->disp1blk_cfg);
- cfg |= (1 << 15);
- lwritel(cfg, &exynos_sysreg->disp1blk_cfg);
+ /*
+ * system register path set
+ * 0: MIE/MDNIE
+ * 1: FIMD Bypass
+ */
+ cfg = lreadl(&exynos_sysreg->disp1blk_cfg);
+ cfg |= (1 << 15);
+ lwritel(cfg, &exynos_sysreg->disp1blk_cfg);
}
void exynos_fimd_lcd_init(vidinfo_t *vid)
diff --git a/src/southbridge/intel/bd82x6x/acpi/platform.asl b/src/southbridge/intel/bd82x6x/acpi/platform.asl
index 0a01e0f..e370668 100644
--- a/src/southbridge/intel/bd82x6x/acpi/platform.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/platform.asl
@@ -48,6 +48,6 @@
Method(_PIC, 1)
{
- // Remember the OS' IRQ routing choice.
- Store(Arg0, PICM)
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
}
diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl
index c5bc48d..1d79aac 100644
--- a/src/southbridge/intel/bd82x6x/acpi/usb.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl
@@ -59,7 +59,7 @@
Store (Arg0, VISI)
Return (PCKG)
- }
+ }
// How many are there?
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
@@ -112,7 +112,7 @@
Store (Arg0, VISI)
Return (PCKG)
- }
+ }
// How many are there?
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 4c45613..8e11f10 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -125,7 +125,7 @@
}
int early_pch_init(const void *gpio_map,
- const struct rcba_config_instruction *rcba_config)
+ const struct rcba_config_instruction *rcba_config)
{
int wake_from_s3;