diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index c69c827..7136cd4 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -497,7 +497,6 @@
 	}
 }
 
-#define HOST_BRIDGE	PCI_DEV(0, 0, 0)
 #define DEFAULT_TCK	TCK_800MHZ
 
 unsigned int get_mem_min_tck(void)
@@ -595,7 +594,7 @@
 
 	mmiosize = get_mmio_size();
 
-	ggc = pci_read_config16(NORTHBRIDGE, GGC);
+	ggc = pci_read_config16(HOST_BRIDGE, GGC);
 	if (!(ggc & 2)) {
 		gfxstolen = ((ggc >> 3) & 0x1f) * 32;
 		gttsize = ((ggc >> 8) & 0x3);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 194e6db..6d3af87 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -136,8 +136,9 @@
 	dimm_info info;
 } ramctr_timing;
 
-#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
-#define NORTHBRIDGE PCI_DEV(0, 0x0, 0)
+#define HOST_BRIDGE	PCI_DEV(0, 0, 0)
+#define SOUTHBRIDGE	PCI_DEV(0, 0x1f, 0)
+
 #define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++)
 #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++)
 #define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank))