soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config option
SF Mask MSRs' Programming which was done under this config
selection will be moved under a new config option called
CAR_HAS_SF_MASKS. This segregates the eNEM programming
sequence based on sub features supported in each processor.
Bug=b:171601324
BRANCH=volteer
Test=Build volteer build and boot on Delbin EVT.
Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 48de0c1..ea4fadb1 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -315,7 +315,7 @@
config USE_CANNONLAKE_CAR_NEM_ENHANCED
bool "Enhanced Non-evict mode"
select SOC_INTEL_COMMON_BLOCK_CAR
- select USE_CAR_NEM_ENHANCED_V1
+ select INTEL_CAR_NEM_ENHANCED
help
A current limitation of NEM (Non-Evict mode) is that code and data
sizes are derived from the requirement to not write out any modified
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 1ec7af5..912760e 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -51,21 +51,6 @@
ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
-config USE_CAR_NEM_ENHANCED_V1
- bool
- select INTEL_CAR_NEM_ENHANCED
- help
- This config supports INTEL_CAR_NEM_ENHANCED mode on
- SKL, KBL, CNL, WHL, CML and ICL and JSL platforms.
-
-config USE_CAR_NEM_ENHANCED_V2
- bool
- select INTEL_CAR_NEM_ENHANCED
- select COS_MAPPED_TO_MSB
- help
- This config supports INTEL_CAR_NEM_ENHANCED mode on
- TGL platform.
-
config COS_MAPPED_TO_MSB
bool
depends on INTEL_CAR_NEM_ENHANCED
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 97bffb0..b60e797 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -415,7 +415,7 @@
mov %ebx, %ecx /* back up the number of ways */
mov %eax, %ebx /* back up the non-eviction mask */
/*
- * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1
+ * Program MSR 0xC91 IA32_L3_MASK_1
* This MSR contain one bit per each way of LLC
* - If this bit is '0' - the way is protected from eviction
* - If this bit is '1' - the way is not protected from eviction
@@ -428,26 +428,18 @@
xor $~0, %eax /* invert 32 bits */
and %ecx, %eax
-#if CONFIG(USE_CAR_NEM_ENHANCED_V1)
movl $IA32_L3_MASK_1, %ecx
-#elif CONFIG(USE_CAR_NEM_ENHANCED_V2)
- movl $IA32_CR_SF_QOS_MASK_1, %ecx
-#endif
xorl %edx, %edx
wrmsr
/*
- * Set MSR 0xC92 IA32_L3_MASK_1 or MSR 0x1892 IA32_CR_SF_QOS_MASK_2
+ * Program MSR 0xC92 IA32_L3_MASK_2
* This MSR contain one bit per each way of LLC
* - If this bit is '0' - the way is protected from eviction
* - If this bit is '1' - the way is not protected from eviction
*/
mov %ebx, %eax
-#if CONFIG(USE_CAR_NEM_ENHANCED_V1)
movl $IA32_L3_MASK_2, %ecx
-#elif CONFIG(USE_CAR_NEM_ENHANCED_V2)
- movl $IA32_CR_SF_QOS_MASK_2, %ecx
-#endif
xorl %edx, %edx
wrmsr
/*
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 4981205..4fe491f 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -170,7 +170,7 @@
config USE_DENVERTON_NS_CAR_NEM_ENHANCED
bool "Enhanced Non-evict mode"
select SOC_INTEL_COMMON_BLOCK_CAR
- select USE_CAR_NEM_ENHANCED_V1
+ select INTEL_CAR_NEM_ENHANCED
help
A current limitation of NEM (Non-Evict mode) is that code and data sizes
are derived from the requirement to not write out any modified cache line.
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 52e9a74..fee52e6 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -23,6 +23,7 @@
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
+ select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
@@ -64,7 +65,6 @@
select DISPLAY_FSP_VERSION_INFO
select HECI_DISABLE_USING_SMM
select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
- select USE_CAR_NEM_ENHANCED_V1
config DCACHE_RAM_BASE
default 0xfef00000
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 294f19f8..0a15f05 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -23,6 +23,7 @@
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
+ select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
@@ -61,7 +62,6 @@
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_202005_BINDING
- select USE_CAR_NEM_ENHANCED_V1
select DISPLAY_FSP_VERSION_INFO
select HECI_DISABLE_USING_SMM
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 3eae5f8..cfc7c52 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -31,6 +31,8 @@
select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT
select HAVE_INTEL_FSP_REPO
+ select INTEL_CAR_NEM_ENHANCED
+ select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_GMA_ACPI
@@ -77,7 +79,6 @@
select TSC_SYNC_MFENCE
select UDELAY_TSC
select UDK_2015_BINDING
- select USE_CAR_NEM_ENHANCED_V1
config FSP_HYPERTHREADING
bool "Enable Hyper-Threading"
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 9340cb7..7629c7e 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -24,7 +24,7 @@
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
- select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM
+ select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP