nb/intel/gm45: Add remaining raminit code to support DDR2
Add the remaining DDR2 code to program the registers for memory
timings, ODT, RCOMP, and refresh mode; and perform receive-enable
calibration.
TEST: DDR2 systems boot
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I6d9a1853fea9e29171d7c2f9ffe7086685c9efad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index c8ec6dc..f28c6d1 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -76,6 +76,15 @@
CHIP_CAP_16G = 6,
} chip_capacity_t;
+typedef enum { /* as in DDR2 spd */
+ REFRESH_15_625 = 0,
+ REFRESH_3_9 = 1,
+ REFRESH_7_8 = 2,
+ REFRESH_31_25 = 3,
+ REFRESH_62_5 = 4,
+ REFRESH_125 = 5,
+} refresh_rate_t;
+
typedef struct {
unsigned int CAS;
fsb_clock_t fsb_clock;
@@ -97,6 +106,7 @@
0xa - 0xf: raw card type A - F */
chip_width_t chip_width;
chip_capacity_t chip_capacity;
+ refresh_rate_t refresh;
unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */
unsigned int banks;
unsigned int ranks;
@@ -411,7 +421,7 @@
void raminit_rcomp_calibration(stepping_t stepping);
void raminit_reset_readwrite_pointers(void);
-void raminit_receive_enable_calibration(const timings_t *, const dimminfo_t *);
+void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
void raminit_read_training(const dimminfo_t *, int s3resume);