Fix MMCONF_SUPPORT_DEFAULT for ramstage
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.
The implementation of pci_default_config() always returned with
pci_cf8_conf1. This means any PCI configuration access that did
not target bus 0 used PCI IO config operations, if PCI MMIO config
was not explicitly requested.
Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3606
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
index eca9390..e6027b7 100644
--- a/src/arch/x86/include/arch/pci_ops.h
+++ b/src/arch/x86/include/arch/pci_ops.h
@@ -7,9 +7,19 @@
extern const struct pci_bus_operations pci_ops_mmconf;
#endif
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+#define pci_bus_default_ops &pci_ops_mmconf
+#else
+#define pci_bus_default_ops &pci_cf8_conf1
+#endif
+
static inline const struct pci_bus_operations *pci_config_default(void)
{
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+ return &pci_ops_mmconf;
+#else
return &pci_cf8_conf1;
+#endif
}
static inline void pci_set_method(device_t dev)
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 4589f6d..ceb1d50 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -1142,11 +1142,7 @@
.enable_resources = amdfam10_domain_enable_resources,
.init = NULL,
.scan_bus = amdfam10_domain_scan_bus,
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 9e5538d..78e9966 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -863,12 +863,7 @@
.enable_resources = domain_enable_resources,
.init = NULL,
.scan_bus = f15_pci_domain_scan_bus,
-
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index f91f690..5eccf43 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -849,12 +849,7 @@
.enable_resources = domain_enable_resources,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
-
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
static void sysconf_init(device_t dev) // first node
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 2228fb5..3f7ca25 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1154,11 +1154,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = amdfam10_domain_scan_bus,
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
static void sysconf_init(device_t dev) // first node
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 3a4439c..687479e 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -202,11 +202,7 @@
.enable_resources = NULL,
.init = mch_domain_init,
.scan_bus = pci_domain_scan_bus,
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 45d967e..9f02734 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -98,11 +98,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c
index 113dc56..01f150e 100644
--- a/src/northbridge/intel/i5000/northbridge.c
+++ b/src/northbridge/intel/i5000/northbridge.c
@@ -168,11 +168,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
static void enable_dev(device_t dev)
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 9d97f0c..7e21164 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -185,11 +185,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
static void mc_read_resources(device_t dev)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index d8e2e9d..e3290d8 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -289,11 +289,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
static void mc_read_resources(device_t dev)
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 06d34d8..600bd13 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -200,11 +200,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
-#else
- .ops_pci_bus = &pci_cf8_conf1,
-#endif
+ .ops_pci_bus = pci_bus_default_ops,
};
static void mc_read_resources(device_t dev)
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index c3c3920..854e175 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -304,8 +304,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
- /* We always run with MMCONF enabled. */
- .ops_pci_bus = &pci_ops_mmconf,
+ .ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)