commit 86e05e8e7309a927271d5dbeca5c83d3a74fe513
author Jon Murphy <jpmurphy@google.com> Thu Jun 08 14:57:51 2023 -0600
committer Eric Lai <eric_lai@quanta.corp-partner.google.com> Tue Jun 13 23:55:27 2023 +0000
tree 21f43c3032c63b27eb845e75c1a4c7b49977eb32
parent 7866166fb4e841f69e0ee73c6e7b2f4ed2ffd542

mb/google/myst: Update PCIe romstage gpios

Update PCIe GPIOs during rom stage to properly initialize the
PCIe devices and allow the NVMe/eMMC to be properly detected.

BUG=b:284213391
TEST=Boot to OS

Change-Id: I24ad6c1addedb414afade2512b6628022d000a47
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/mainboard/google/myst/port_descriptors.c

diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c
index 108dd4e..6d0d0d6 100644
--- a/src/mainboard/google/myst/port_descriptors.c
+++ b/src/mainboard/google/myst/port_descriptors.c
@@ -54,8 +54,6 @@
 	.function_number = PCI_FUNC(NVME_DEVFN),
 	.link_speed_capability = GEN_MAX,
 	.turn_off_unused_lanes = true,
-	/* TODO(b/284213391): Fix PCIe shutdown */
-	.link_hotplug = 3,
 	.clk_req = CLK_REQ3,
 };
 
@@ -68,8 +66,6 @@
 	.function_number = PCI_FUNC(NVME_DEVFN),
 	.link_speed_capability = GEN_MAX,
 	.turn_off_unused_lanes = true,
-	/* TODO(b/284213391): Fix PCIe shutdown */
-	.link_hotplug = 3,
 	.clk_req = CLK_REQ3,
 };
 

src/mainboard/google/myst/variants/baseboard/gpio.c

diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c
index efd654e..f97cc16 100644
--- a/src/mainboard/google/myst/variants/baseboard/gpio.c
+++ b/src/mainboard/google/myst/variants/baseboard/gpio.c
@@ -196,8 +196,22 @@
 /* PCIE_RST needs to be brought high before FSP-M runs */
 static const struct soc_amd_gpio romstage_gpio_table[] = {
 	/* Deassert all AUX_RESET lines & PCIE_RST */
+	/* SD_AUX_RST */
+	PAD_GPO(GPIO_29, LOW),
+	/* SSD_AUX_RESET */
+	PAD_GPO(GPIO_31, LOW),
 	/* WLAN_AUX_RST_L (ACTIVE LOW) */
 	PAD_GPO(GPIO_38, HIGH),
+	/* WWAN_AUX_RST_L (ACTIVE LOW) */
+	PAD_GPO(GPIO_39, HIGH),
+	/* CLK_REQ0_L / WLAN */
+	PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
+	/* CLK_REQ1_L / SD */
+	PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE),
+	/* CLK_REQ2_L / WWAN */
+	PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
+	/* CLK_REQ3_L / SSD */
+	PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE),
 	/* PCIE_RST0_L */
 	PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
 };