mb/google/guybrush: Enable guybrush variant

Enable the building of guybrush variants and configure the first variant
also called guybrush.

BUG=b:180419462
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 4e6e21c..e96b4dc 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -38,10 +38,18 @@
 	help
 	  TODO: might need to be adapted for better placement of files in cbfs
 
+config VARIANT_DIR
+	string
+	default "guybrush" if BOARD_GOOGLE_GUYBRUSH
+
 config DEVICETREE
 	string
 	default "variants/baseboard/devicetree.cb"
 
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
 config MAINBOARD_FAMILY
 	string
 	default "Google_Guybrush"
diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc
index d16a874..7d2b135 100644
--- a/src/mainboard/google/guybrush/Makefile.inc
+++ b/src/mainboard/google/guybrush/Makefile.inc
@@ -6,4 +6,7 @@
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 subdirs-y += variants/baseboard
+subdirs-y += variants/$(VARIANT_DIR)
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
new file mode 100644
index 0000000..519bd07
--- /dev/null
+++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+chip soc/amd/cezanne
+	device domain 0 on
+	end # domain
+end	# chip soc/amd/cezanne