doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes
Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
index 6b629f4..b6c927e 100644
--- a/Documentation/releases/coreboot-4.14-relnotes.md
+++ b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -61,4 +61,19 @@
moved to the common AMD SoC code, so that they could be used by the
Cezanne code instead of adding another slightly different copy.
+### X86 bootblock layout
+
+The static size C_ENV_BOOTBLOCK_SIZE was mostly dropped in favor of
+dynamically allocating the stage size; the Kconfig is still available
+to use as a fixed size and to enforce a maximum for selected chipsets.
+Linker sections are now top-aligned for a reduced flash footprint and to
+maintain the requirements of near jump from reset vector.
+
+### ACPI GNVS framework
+
+SMI handlers for APM_CNT_GNVS_UDPATE were dropped; GNVS pointer to SMM is
+now passed from within SMM_MODULE_LOADER. Allocation and initialisations
+for common ACPI GNVS table entries were largely moved to one centralized
+implementation.
+
### Add significant changes here