src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL
Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.
During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x
are not being reset to default as
per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5.
Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient.
Bug=b:171601324
BRANCH=volteer
Test=Build and boot to ChromeOS on Delbin.
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 912760e..2b630d0 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -51,6 +51,14 @@
ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
+config CAR_HAS_SF_MASKS
+ bool
+ depends on INTEL_CAR_NEM_ENHANCED
+ help
+ In the case of non-inclusive cache architecture Snoop Filter MSR
+ IA32_L3_SF_MASK_x programming is required along with the data ways.
+ This is applicable for TGL and beyond.
+
config COS_MAPPED_TO_MSB
bool
depends on INTEL_CAR_NEM_ENHANCED
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index b60e797..aaf6af7 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -412,8 +412,27 @@
subl $0x01, %eax
set_eviction_mask:
- mov %ebx, %ecx /* back up the number of ways */
- mov %eax, %ebx /* back up the non-eviction mask */
+ mov %ebx, %ecx /* back up number of ways */
+ mov %eax, %ebx /* back up the non-eviction mask*/
+#if CONFIG(CAR_HAS_SF_MASKS)
+ mov %ecx, %edi /* use number of ways to prepare SF mask */
+ /*
+ * SF mask is programmed with the double number of bits than
+ * the number of ways
+ */
+ mov $0x01, %eax
+ shl %cl, %eax
+ shl %cl, %eax
+ subl $0x01, %eax /* contains SF mask */
+ /*
+ * Program MSR 0x1891 IA32_CR_SF_QOS_MASK_1 with
+ * total number of LLC ways
+ */
+ movl $IA32_CR_SF_QOS_MASK_1, %ecx
+ xorl %edx, %edx
+ wrmsr
+ mov %edi, %ecx /* restore number of ways */
+#endif
/*
* Program MSR 0xC91 IA32_L3_MASK_1
* This MSR contain one bit per each way of LLC
@@ -431,7 +450,6 @@
movl $IA32_L3_MASK_1, %ecx
xorl %edx, %edx
wrmsr
-
/*
* Program MSR 0xC92 IA32_L3_MASK_2
* This MSR contain one bit per each way of LLC
@@ -460,7 +478,6 @@
movl $0x02, %eax
#endif
wrmsr
-
movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 7629c7e..c7e10a9 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -25,6 +25,7 @@
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
+ select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED
select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP