diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index c7ee582..8fe1df3 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -173,10 +173,10 @@
 	/* Set up SMRR. */
 	smrr.lo = relo_attrs.smrr_base;
 	smrr.hi = 0;
-	wrmsr(SMRRphysBase_MSR, smrr);
+	wrmsr(SMRR_PHYS_BASE, smrr);
 	smrr.lo = relo_attrs.smrr_mask;
 	smrr.hi = 0;
-	wrmsr(SMRRphysMask_MSR, smrr);
+	wrmsr(SMRR_PHYS_MASK, smrr);
 
 	/* The relocated handler runs with all CPUs concurrently. Therefore
 	 * stagger the entry points adjusting SMBASE downwards by save state
@@ -243,7 +243,7 @@
 	relo_attrs.smbase = (uint32_t)smm_region_start();
 	relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
 	relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask;
-	relo_attrs.smrr_mask |= MTRRphysMaskValid;
+	relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
 
 	/* Install handlers. */
 	if (install_relocation_handler(pattrs->num_cpus) < 0) {