cpu/mtrr.h: Fix macro names for MTRR registers
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 98671f4..17364de 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -81,15 +81,15 @@
/* Enable caching for 0 - coreboot ram using variable mtrr */
msr.lo = 0 | MTRR_TYPE_WRBACK;
msr.hi = 0;
- wrmsr(MTRRphysBase_MSR(0), msr);
- msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid;
+ wrmsr(MTRR_PHYS_BASE(0), msr);
+ msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRRphysMask_MSR(0), msr);
+ wrmsr(MTRR_PHYS_MASK(0), msr);
/* Set the default memory type and disable fixed and enable variable MTRRs */
msr.hi = 0;
msr.lo = (1 << 11);
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
enable_cache();
}
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 133daac..0b2bc60 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -76,9 +76,9 @@
cvtsd2si %xmm3, %ebx
/* Check if cpu_init_detected. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- andl $MTRRdefTypeEn, %eax
+ andl $MTRR_DEF_TYPE_EN, %eax
movl %eax, %ebx /* We store the status. */
jmp_if_k8(CAR_FAM10_out_post_errata)
@@ -270,27 +270,27 @@
#if CacheSize > 0x8000
/* Enable caching for 32K-64K using fixed MTRR. */
- movl $MTRRfix4K_C0000_MSR, %ecx
+ movl $MTRR_FIX_4K_C0000, %ecx
simplemask CacheSize, 0x8000
wrmsr
#endif
#if CacheSize > 0x10000
/* Enable caching for 64K-96K using fixed MTRR. */
- movl $MTRRfix4K_D0000_MSR, %ecx
+ movl $MTRR_FIX_4K_D0000, %ecx
simplemask CacheSize, 0x10000
wrmsr
#endif
#if CacheSize > 0x18000
/* Enable caching for 96K-128K using fixed MTRR. */
- movl $MTRRfix4K_D8000_MSR, %ecx
+ movl $MTRR_FIX_4K_D8000, %ecx
simplemask CacheSize, 0x18000
wrmsr
#endif
/* Enable caching for 0-32K using fixed MTRR. */
- movl $MTRRfix4K_C8000_MSR, %ecx
+ movl $MTRR_FIX_4K_C8000, %ecx
simplemask CacheSize, 0
wrmsr
@@ -305,7 +305,7 @@
/* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -316,19 +316,19 @@
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
jmp_if_k8(wbcache_post_fam10_setup)
movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
wbcache_post_fam10_setup:
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
/* Set the default memory type and enable fixed and variable MTRRs. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx
- movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
+ movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
wrmsr
/* Enable the MTRRs and IORRs in SYSCFG. */
@@ -462,35 +462,35 @@
all_mtrr_msrs:
/* fixed MTRR MSRs */
- .long MTRRfix64K_00000_MSR
- .long MTRRfix16K_80000_MSR
- .long MTRRfix16K_A0000_MSR
- .long MTRRfix4K_C0000_MSR
- .long MTRRfix4K_C8000_MSR
- .long MTRRfix4K_D0000_MSR
- .long MTRRfix4K_D8000_MSR
- .long MTRRfix4K_E0000_MSR
- .long MTRRfix4K_E8000_MSR
- .long MTRRfix4K_F0000_MSR
- .long MTRRfix4K_F8000_MSR
+ .long MTRR_FIX_64K_00000
+ .long MTRR_FIX_16K_80000
+ .long MTRR_FIX_16K_A0000
+ .long MTRR_FIX_4K_C0000
+ .long MTRR_FIX_4K_C8000
+ .long MTRR_FIX_4K_D0000
+ .long MTRR_FIX_4K_D8000
+ .long MTRR_FIX_4K_E0000
+ .long MTRR_FIX_4K_E8000
+ .long MTRR_FIX_4K_F0000
+ .long MTRR_FIX_4K_F8000
/* var MTRR MSRs */
- .long MTRRphysBase_MSR(0)
- .long MTRRphysMask_MSR(0)
- .long MTRRphysBase_MSR(1)
- .long MTRRphysMask_MSR(1)
- .long MTRRphysBase_MSR(2)
- .long MTRRphysMask_MSR(2)
- .long MTRRphysBase_MSR(3)
- .long MTRRphysMask_MSR(3)
- .long MTRRphysBase_MSR(4)
- .long MTRRphysMask_MSR(4)
- .long MTRRphysBase_MSR(5)
- .long MTRRphysMask_MSR(5)
- .long MTRRphysBase_MSR(6)
- .long MTRRphysMask_MSR(6)
- .long MTRRphysBase_MSR(7)
- .long MTRRphysMask_MSR(7)
+ .long MTRR_PHYS_BASE(0)
+ .long MTRR_PHYS_MASK(0)
+ .long MTRR_PHYS_BASE(1)
+ .long MTRR_PHYS_MASK(1)
+ .long MTRR_PHYS_BASE(2)
+ .long MTRR_PHYS_MASK(2)
+ .long MTRR_PHYS_BASE(3)
+ .long MTRR_PHYS_MASK(3)
+ .long MTRR_PHYS_BASE(4)
+ .long MTRR_PHYS_MASK(4)
+ .long MTRR_PHYS_BASE(5)
+ .long MTRR_PHYS_MASK(5)
+ .long MTRR_PHYS_BASE(6)
+ .long MTRR_PHYS_MASK(6)
+ .long MTRR_PHYS_BASE(7)
+ .long MTRR_PHYS_MASK(7)
/* Variable IORR MTRR MSRs */
.long IORRBase_MSR(0)
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index d3a3812..3b464b8 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -33,15 +33,15 @@
msr.lo = 0;
msr.hi = 0;
- wrmsr(MTRRfix4K_C8000_MSR, msr);
+ wrmsr(MTRR_FIX_4K_C8000, msr);
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
- wrmsr(MTRRfix4K_C0000_MSR, msr);
+ wrmsr(MTRR_FIX_4K_C0000, msr);
#endif
#if CONFIG_DCACHE_RAM_SIZE > 0x10000
- wrmsr(MTRRfix4K_D0000_MSR, msr);
+ wrmsr(MTRR_FIX_4K_D0000, msr);
#endif
#if CONFIG_DCACHE_RAM_SIZE > 0x18000
- wrmsr(MTRRfix4K_D8000_MSR, msr);
+ wrmsr(MTRR_FIX_4K_D8000, msr);
#endif
/* disable fixed mtrr from now on, it will be enabled by ramstage again*/
@@ -53,7 +53,7 @@
msr.hi = 0;
msr.lo = (1 << 11);
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
enable_cache();
}
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index a6561ee..268f1b2 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -105,12 +105,12 @@
{
int i;
for (i = 0; i < MTRR_COUNT; i++) {
- state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i));
- state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i));
+ state->mtrrs[i].base = rdmsr(MTRR_PHYS_BASE(i));
+ state->mtrrs[i].mask = rdmsr(MTRR_PHYS_MASK(i));
}
state->top_mem = rdmsr(TOP_MEM);
state->top_mem2 = rdmsr(TOP_MEM2);
- state->def_type = rdmsr(MTRRdefType_MSR);
+ state->def_type = rdmsr(MTRR_DEF_TYPE_MSR);
}
static void restore_mtrr_state(struct mtrr_state *state)
@@ -119,12 +119,12 @@
disable_cache();
for (i = 0; i < MTRR_COUNT; i++) {
- wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base);
- wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask);
+ wrmsr(MTRR_PHYS_BASE(i), state->mtrrs[i].base);
+ wrmsr(MTRR_PHYS_MASK(i), state->mtrrs[i].mask);
}
wrmsr(TOP_MEM, state->top_mem);
wrmsr(TOP_MEM2, state->top_mem2);
- wrmsr(MTRRdefType_MSR, state->def_type);
+ wrmsr(MTRR_DEF_TYPE_MSR, state->def_type);
enable_cache();
}
@@ -158,22 +158,22 @@
for (i = 0; i < MTRR_COUNT; i++) {
msr_t zero;
zero.lo = zero.hi = 0;
- wrmsr(MTRRphysBase_MSR(i), zero);
- wrmsr(MTRRphysMask_MSR(i), zero);
+ wrmsr(MTRR_PHYS_BASE(i), zero);
+ wrmsr(MTRR_PHYS_MASK(i), zero);
}
/* Write back cache the first 1MB */
msr.hi = 0x00000000;
msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
- wrmsr(MTRRphysBase_MSR(0), msr);
+ wrmsr(MTRR_PHYS_BASE(0), msr);
msr.hi = 0x000000ff;
msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
- wrmsr(MTRRphysMask_MSR(0), msr);
+ wrmsr(MTRR_PHYS_MASK(0), msr);
/* Set the default type to write combining */
msr.hi = 0x00000000;
msr.lo = 0xc00 | MTRR_TYPE_WRCOMB;
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
/* Set TOP_MEM to 4G */
msr.hi = 0x00000001;
diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c
index 943fd97..88b5713 100644
--- a/src/cpu/amd/pi/s3_resume.c
+++ b/src/cpu/amd/pi/s3_resume.c
@@ -271,15 +271,15 @@
/* Enable caching for 0 - coreboot ram using variable mtrr */
msr.lo = 0 | MTRR_TYPE_WRBACK;
msr.hi = 0;
- wrmsr(MTRRphysBase_MSR(0), msr);
- msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid;
+ wrmsr(MTRR_PHYS_BASE(0), msr);
+ msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRRphysMask_MSR(0), msr);
+ wrmsr(MTRR_PHYS_MASK(0), msr);
/* Set the default memory type and disable fixed and enable variable MTRRs */
msr.hi = 0;
msr.lo = (1 << 11);
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
enable_cache();
}
diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c
index 2e9a4c9..e13f24f 100644
--- a/src/cpu/amd/smm/smm_init.c
+++ b/src/cpu/amd/smm/smm_init.c
@@ -39,7 +39,7 @@
/* Back up MSRs for later restore */
syscfg_orig = rdmsr(SYSCFG_MSR);
- mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR);
+ mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000);
/* MTRR changes don't like an enabled cache */
disable_cache();
@@ -57,7 +57,7 @@
/* set DRAM access to 0xa0000 */
msr.lo = 0x18181818;
msr.hi = 0x18181818;
- wrmsr(MTRRfix16K_A0000_MSR, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
/* enable the extended features */
msr = syscfg_orig;
@@ -73,7 +73,7 @@
/* Restore SYSCFG and MTRR */
wrmsr(SYSCFG_MSR, syscfg_orig);
- wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig);
+ wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig);
enable_cache();
/* CPU MSR are set in CPU init */
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index f9be6e8..6ef8604 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -54,7 +54,7 @@
*/
xorl %eax, %eax
xorl %edx, %edx
- movl $MTRRfix64K_00000_MSR, %ecx
+ movl $MTRR_FIX_64K_00000, %ecx
wrmsr
/*
@@ -102,16 +102,16 @@
/* Wait for the Logical AP to complete initialization. */
LogicalAP_SIPINotdone:
- movl $MTRRfix64K_00000_MSR, %ecx
+ movl $MTRR_FIX_64K_00000, %ecx
rdmsr
orl %eax, %eax
jz LogicalAP_SIPINotdone
NotHtProcessor:
/* Set the default memory type and enable fixed and variable MTRRs. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx
- movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
+ movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
wrmsr
/* Clear all MTRRs. */
@@ -131,35 +131,35 @@
all_mtrr_msrs:
/* fixed MTRR MSRs */
- .long MTRRfix64K_00000_MSR
- .long MTRRfix16K_80000_MSR
- .long MTRRfix16K_A0000_MSR
- .long MTRRfix4K_C0000_MSR
- .long MTRRfix4K_C8000_MSR
- .long MTRRfix4K_D0000_MSR
- .long MTRRfix4K_D8000_MSR
- .long MTRRfix4K_E0000_MSR
- .long MTRRfix4K_E8000_MSR
- .long MTRRfix4K_F0000_MSR
- .long MTRRfix4K_F8000_MSR
+ .long MTRR_FIX_64K_00000
+ .long MTRR_FIX_16K_80000
+ .long MTRR_FIX_16K_A0000
+ .long MTRR_FIX_4K_C0000
+ .long MTRR_FIX_4K_C8000
+ .long MTRR_FIX_4K_D0000
+ .long MTRR_FIX_4K_D8000
+ .long MTRR_FIX_4K_E0000
+ .long MTRR_FIX_4K_E8000
+ .long MTRR_FIX_4K_F0000
+ .long MTRR_FIX_4K_F8000
/* var MTRR MSRs */
- .long MTRRphysBase_MSR(0)
- .long MTRRphysMask_MSR(0)
- .long MTRRphysBase_MSR(1)
- .long MTRRphysMask_MSR(1)
- .long MTRRphysBase_MSR(2)
- .long MTRRphysMask_MSR(2)
- .long MTRRphysBase_MSR(3)
- .long MTRRphysMask_MSR(3)
- .long MTRRphysBase_MSR(4)
- .long MTRRphysMask_MSR(4)
- .long MTRRphysBase_MSR(5)
- .long MTRRphysMask_MSR(5)
- .long MTRRphysBase_MSR(6)
- .long MTRRphysMask_MSR(6)
- .long MTRRphysBase_MSR(7)
- .long MTRRphysMask_MSR(7)
+ .long MTRR_PHYS_BASE(0)
+ .long MTRR_PHYS_MASK(0)
+ .long MTRR_PHYS_BASE(1)
+ .long MTRR_PHYS_MASK(1)
+ .long MTRR_PHYS_BASE(2)
+ .long MTRR_PHYS_MASK(2)
+ .long MTRR_PHYS_BASE(3)
+ .long MTRR_PHYS_MASK(3)
+ .long MTRR_PHYS_BASE(4)
+ .long MTRR_PHYS_MASK(4)
+ .long MTRR_PHYS_BASE(5)
+ .long MTRR_PHYS_MASK(5)
+ .long MTRR_PHYS_BASE(6)
+ .long MTRR_PHYS_MASK(6)
+ .long MTRR_PHYS_BASE(7)
+ .long MTRR_PHYS_MASK(7)
.long 0x000 /* NULL, end of table */
@@ -219,13 +219,13 @@
#if CacheSize > 0x8000
/* Enable caching for 32K-64K using fixed MTRR. */
- movl $MTRRfix4K_C0000_MSR, %ecx
+ movl $MTRR_FIX_4K_C0000, %ecx
simplemask CacheSize, 0x8000
wrmsr
#endif
/* Enable caching for 0-32K using fixed MTRR. */
- movl $MTRRfix4K_C8000_MSR, %ecx
+ movl $MTRR_FIX_4K_C8000, %ecx
simplemask CacheSize, 0
wrmsr
@@ -235,7 +235,7 @@
* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -246,9 +246,9 @@
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
movl $0x0000000f, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
@@ -332,13 +332,13 @@
movl %eax, %cr0
/* Clear sth. */
- movl $MTRRfix4K_C8000_MSR, %ecx
+ movl $MTRR_FIX_4K_C8000, %ecx
xorl %edx, %edx
xorl %eax, %eax
wrmsr
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
- movl $MTRRfix4K_C0000_MSR, %ecx
+ movl $MTRR_FIX_4K_C0000, %ecx
wrmsr
#endif
@@ -346,9 +346,9 @@
* Set the default memory type and disable fixed
* and enable variable MTRRs.
*/
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx
- movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */
+ movl $MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */
wrmsr
/* Enable cache. */
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 193ad41..6eb50ba 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -61,7 +61,7 @@
post_code(0x21)
/* Configure the default memory type to uncacheable. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~0x00000cff), %eax
wrmsr
@@ -95,9 +95,9 @@
*/
addrsize_set_high:
xorl %eax, %eax
- movl $MTRRphysMask_MSR(0), %ecx
+ movl $MTRR_PHYS_MASK(0), %ecx
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
movl $LAPIC_BASE_MSR, %ecx
not %edx
@@ -188,7 +188,7 @@
post_code(0x26)
/* Wait for sibling CPU to start. */
-1: movl $(MTRRphysBase_MSR(0)), %ecx
+1: movl $(MTRR_PHYS_BASE(0)), %ecx
rdmsr
andl %eax, %eax
jnz sipi_complete
@@ -211,7 +211,7 @@
post_code(0x28)
/* MTRR registers are shared between HT siblings. */
- movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(1<<12), %eax
xorl %edx, %edx
wrmsr
@@ -230,21 +230,21 @@
post_code(0x2a)
/* Set Cache-as-RAM base address. */
- movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
/* Set Cache-as-RAM mask. */
- movl $(MTRRphysMask_MSR(0)), %ecx
+ movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
post_code(0x2b)
@@ -308,7 +308,7 @@
#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -319,9 +319,9 @@
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
@@ -356,9 +356,9 @@
post_code(0x34)
/* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- andl $(~MTRRdefTypeEn), %eax
+ andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
post_code(0x35)
@@ -382,24 +382,24 @@
post_code(0x38)
/* Enable Write Back and Speculative Reads for low RAM. */
- movl $MTRRphysBase_MSR(0), %ecx
+ movl $MTRR_PHYS_BASE(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
+ movl $MTRR_PHYS_MASK(0), %ecx
rdmsr
- movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#if CACHE_ROM_SIZE
/* Enable caching and Speculative Reads for Flash ROM device. */
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
- movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#endif
@@ -413,9 +413,9 @@
post_code(0x3a)
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
post_code(0x3b)
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c
index a685eaa..ef94991 100644
--- a/src/cpu/intel/fsp_model_406dx/bootblock.c
+++ b/src/cpu/intel/fsp_model_406dx/bootblock.c
@@ -56,10 +56,10 @@
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
- wrmsr(MTRRphysBase_MSR(reg), basem);
- maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+ wrmsr(MTRR_PHYS_BASE(reg), basem);
+ maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRRphysMask_MSR(reg), maskm);
+ wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
@@ -74,7 +74,7 @@
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void set_no_evict_mode_msr(void)
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index f5d0f6c..8d0c53c 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -44,10 +44,10 @@
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
- wrmsr(MTRRphysBase_MSR(reg), basem);
- maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+ wrmsr(MTRR_PHYS_BASE(reg), basem);
+ maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRRphysMask_MSR(reg), maskm);
+ wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
@@ -61,7 +61,7 @@
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void set_flex_ratio_to_tdp_nominal(void)
@@ -113,12 +113,12 @@
static void check_for_clean_reset(void)
{
msr_t msr;
- msr = rdmsr(MTRRdefType_MSR);
+ msr = rdmsr(MTRR_DEF_TYPE_MSR);
/* Use the MTRR default type MSR as a proxy for detecting INIT#.
* Reset the system if any known bits are set in that MSR. That is
* an indication of the CPU not being properly reset. */
- if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) {
+ if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) {
outb(0x0, 0xcf9);
outb(0x6, 0xcf9);
halt();
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 0978bfb..b8df2a1 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -73,31 +73,31 @@
post_code(0x22)
/* Configure the default memory type to uncacheable. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~0x00000cff), %eax
wrmsr
post_code(0x23)
/* Set Cache-as-RAM base address. */
- movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
post_code(0x24)
/* Set Cache-as-RAM mask. */
- movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(MTRR_PHYS_MASK(0)), %ecx
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(0x25)
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
@@ -134,7 +134,7 @@
movl %eax, %cr0
/* Enable cache for our code in Flash because we do XIP here */
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -145,19 +145,19 @@
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
movl $CPU_PHYSMASK_HI, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
post_code(0x27)
/* Enable caching for ram init code to run faster */
- movl $MTRRphysBase_MSR(2), %ecx
+ movl $MTRR_PHYS_BASE(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
- movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+ movl $MTRR_PHYS_MASK(2), %ecx
+ movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
@@ -197,9 +197,9 @@
post_code(0x31)
/* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- andl $(~MTRRdefTypeEn), %eax
+ andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
post_code(0x31)
@@ -220,9 +220,9 @@
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
- movl $MTRRphysBase_MSR(2), %ecx
+ movl $MTRR_PHYS_BASE(2), %ecx
wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
+ movl $MTRR_PHYS_MASK(2), %ecx
wrmsr
post_code(0x33)
@@ -246,7 +246,7 @@
/* Get number of MTRRs. */
popl %ebx
- movl $MTRRphysBase_MSR(0), %ecx
+ movl $MTRR_PHYS_BASE(0), %ecx
1:
testl %ebx, %ebx
jz 1f
@@ -279,9 +279,9 @@
post_code(0x3a)
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
post_code(0x3b)
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 9c238ca..3bb1090 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -117,14 +117,14 @@
/* Cache the ROM as WP just below 4GiB. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;
@@ -135,7 +135,7 @@
* be 8MiB aligned. Set this area as cacheable so it can be used later
* for ramstage before setting up the entire RAM as cacheable. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
num_mtrrs++;
@@ -146,7 +146,7 @@
* to cacheable it provides faster access when relocating the SMM
* handler as well as using the TSEG region for other purposes. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
+ slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
num_mtrrs++;
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index ab94f9a..00e2d55 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -73,8 +73,8 @@
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
- wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
+ wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_emrr(struct smm_relocation_params *relo_params)
@@ -214,7 +214,7 @@
update_save_state(cpu, relo_params, runtime);
/* Write EMRR and SMRR MSRs based on indicated support. */
- mtrr_cap = rdmsr(MTRRcap_MSR);
+ mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED)
write_smrr(relo_params);
@@ -272,7 +272,7 @@
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
- params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
@@ -283,14 +283,14 @@
* on the number of physical address bits supported. */
params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
params->emrr_base.hi = 0;
- params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
params->uncore_emrr_base.lo = emrr_base;
params->uncore_emrr_base.hi = 0;
params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
- MTRRphysMaskValid;
+ MTRR_PHYS_MASK_VALID;
params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
}
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index b6a2442..edffe14 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -43,10 +43,10 @@
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
- wrmsr(MTRRphysBase_MSR(reg), basem);
- maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+ wrmsr(MTRR_PHYS_BASE(reg), basem);
+ maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRRphysMask_MSR(reg), maskm);
+ wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
@@ -60,7 +60,7 @@
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void set_flex_ratio_to_tdp_nominal(void)
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index cfa3b6b..f36af2b 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -48,8 +48,8 @@
jc wait_for_sipi
post_code(0x21)
- /* Clean-up MTRRdefType_MSR. */
- movl $MTRRdefType_MSR, %ecx
+ /* Clean-up MTRR_DEF_TYPE_MSR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %eax, %eax
xorl %edx, %edx
wrmsr
@@ -69,7 +69,7 @@
jnz clear_mtrrs
/* Zero out all variable range MTRRs. */
- movl $MTRRcap_MSR, %ecx
+ movl $MTRR_CAP_MSR, %ecx
rdmsr
andl $0xff, %eax
shl $1, %eax
@@ -85,24 +85,24 @@
post_code(0x23)
/* Set Cache-as-RAM base address. */
- movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
post_code(0x24)
/* Set Cache-as-RAM mask. */
- movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(MTRR_PHYS_MASK(0)), %ecx
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(0x25)
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
@@ -139,7 +139,7 @@
movl %eax, %cr0
/* Enable cache for our code in Flash because we do XIP here */
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -150,9 +150,9 @@
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
movl $CPU_PHYSMASK_HI, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
post_code(0x27)
@@ -189,9 +189,9 @@
post_code(0x31)
/* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- andl $(~MTRRdefTypeEn), %eax
+ andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
post_code(0x31)
@@ -228,12 +228,12 @@
/* Enable Write Back and Speculative Reads for the first MB
* and ramstage.
*/
- movl $MTRRphysBase_MSR(0), %ecx
+ movl $MTRR_PHYS_BASE(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+ movl $MTRR_PHYS_MASK(0), %ecx
+ movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
@@ -241,12 +241,12 @@
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $MTRR_PHYS_MASK(1), %ecx
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
@@ -261,9 +261,9 @@
post_code(0x3a)
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
post_code(0x3b)
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index d41afb2..416b484 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -44,10 +44,10 @@
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
- wrmsr(MTRRphysBase_MSR(reg), basem);
- maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+ wrmsr(MTRR_PHYS_BASE(reg), basem);
+ maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRRphysMask_MSR(reg), maskm);
+ wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
@@ -61,7 +61,7 @@
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void set_flex_ratio_to_tdp_nominal(void)
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index a3f1c64..04c0808 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -68,31 +68,31 @@
post_code(0x22)
/* Configure the default memory type to uncacheable. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~0x00000cff), %eax
wrmsr
post_code(0x23)
/* Set Cache-as-RAM base address. */
- movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
post_code(0x24)
/* Set Cache-as-RAM mask. */
- movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(MTRR_PHYS_MASK(0)), %ecx
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(0x25)
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
@@ -129,7 +129,7 @@
movl %eax, %cr0
/* Enable cache for our code in Flash because we do XIP here */
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -140,19 +140,19 @@
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
movl $CPU_PHYSMASK_HI, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
post_code(0x27)
/* Enable caching for ram init code to run faster */
- movl $MTRRphysBase_MSR(2), %ecx
+ movl $MTRR_PHYS_BASE(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
- movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+ movl $MTRR_PHYS_MASK(2), %ecx
+ movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
@@ -189,9 +189,9 @@
post_code(0x31)
/* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- andl $(~MTRRdefTypeEn), %eax
+ andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
post_code(0x31)
@@ -212,9 +212,9 @@
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
- movl $MTRRphysBase_MSR(2), %ecx
+ movl $MTRR_PHYS_BASE(2), %ecx
wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
+ movl $MTRR_PHYS_MASK(2), %ecx
wrmsr
post_code(0x33)
@@ -236,12 +236,12 @@
/* Enable Write Back and Speculative Reads for the first MB
* and ramstage.
*/
- movl $MTRRphysBase_MSR(0), %ecx
+ movl $MTRR_PHYS_BASE(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+ movl $MTRR_PHYS_MASK(0), %ecx
+ movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
@@ -249,12 +249,12 @@
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $MTRR_PHYS_MASK(1), %ecx
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
@@ -269,9 +269,9 @@
post_code(0x3a)
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
post_code(0x3b)
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 271b756..16244fb 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -52,27 +52,27 @@
jnz clear_mtrrs
/* Configure the default memory type to uncacheable. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~0x00000cff), %eax
wrmsr
/* Set Cache-as-RAM base address. */
- movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(MTRR_PHYS_BASE(0)), %ecx
movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
/* Set Cache-as-RAM mask. */
- movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(MTRR_PHYS_MASK(0)), %ecx
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Enable L2 cache. */
@@ -102,7 +102,7 @@
#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -113,9 +113,9 @@
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
movl $CPU_PHYSMASK_HI, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
@@ -150,9 +150,9 @@
post_code(0x31)
/* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- andl $(~MTRRdefTypeEn), %eax
+ andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
post_code(0x31)
@@ -176,23 +176,23 @@
post_code(0x38)
/* Enable Write Back and Speculative Reads for low RAM. */
- movl $MTRRphysBase_MSR(0), %ecx
+ movl $MTRR_PHYS_BASE(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+ movl $MTRR_PHYS_MASK(0), %ecx
+ movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#if CACHE_ROM_SIZE
/* Enable caching and Speculative Reads for Flash ROM device. */
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $MTRR_PHYS_MASK(1), %ecx
+ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
@@ -207,9 +207,9 @@
post_code(0x3a)
/* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
post_code(0x3b)
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index bc14444..41ec39c 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -63,8 +63,8 @@
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
- wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
+ wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
}
/* The relocation work is actually performed in SMM context, but the code
@@ -109,7 +109,7 @@
save_state->smbase, save_state->iedbase, save_state);
/* Write SMRR MSRs based on indicated support. */
- mtrr_cap = rdmsr(MTRRcap_MSR);
+ mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED)
write_smrr(relo_params);
@@ -142,7 +142,7 @@
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
- params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
}
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index e8a4ee2..cc91c6e 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -44,9 +44,9 @@
invd
/* Set the default memory type and enable fixed and variable MTRRs. */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx
- movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
+ movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
wrmsr
/* Clear all MTRRs. */
@@ -66,55 +66,55 @@
all_mtrr_msrs:
/* fixed MTRR MSRs */
- .long MTRRfix64K_00000_MSR
- .long MTRRfix16K_80000_MSR
- .long MTRRfix16K_A0000_MSR
- .long MTRRfix4K_C0000_MSR
- .long MTRRfix4K_C8000_MSR
- .long MTRRfix4K_D0000_MSR
- .long MTRRfix4K_D8000_MSR
- .long MTRRfix4K_E0000_MSR
- .long MTRRfix4K_E8000_MSR
- .long MTRRfix4K_F0000_MSR
- .long MTRRfix4K_F8000_MSR
+ .long MTRR_FIX_64K_00000
+ .long MTRR_FIX_16K_80000
+ .long MTRR_FIX_16K_A0000
+ .long MTRR_FIX_4K_C0000
+ .long MTRR_FIX_4K_C8000
+ .long MTRR_FIX_4K_D0000
+ .long MTRR_FIX_4K_D8000
+ .long MTRR_FIX_4K_E0000
+ .long MTRR_FIX_4K_E8000
+ .long MTRR_FIX_4K_F0000
+ .long MTRR_FIX_4K_F8000
/* var MTRR MSRs */
- .long MTRRphysBase_MSR(0)
- .long MTRRphysMask_MSR(0)
- .long MTRRphysBase_MSR(1)
- .long MTRRphysMask_MSR(1)
- .long MTRRphysBase_MSR(2)
- .long MTRRphysMask_MSR(2)
- .long MTRRphysBase_MSR(3)
- .long MTRRphysMask_MSR(3)
- .long MTRRphysBase_MSR(4)
- .long MTRRphysMask_MSR(4)
- .long MTRRphysBase_MSR(5)
- .long MTRRphysMask_MSR(5)
- .long MTRRphysBase_MSR(6)
- .long MTRRphysMask_MSR(6)
- .long MTRRphysBase_MSR(7)
- .long MTRRphysMask_MSR(7)
+ .long MTRR_PHYS_BASE(0)
+ .long MTRR_PHYS_MASK(0)
+ .long MTRR_PHYS_BASE(1)
+ .long MTRR_PHYS_MASK(1)
+ .long MTRR_PHYS_BASE(2)
+ .long MTRR_PHYS_MASK(2)
+ .long MTRR_PHYS_BASE(3)
+ .long MTRR_PHYS_MASK(3)
+ .long MTRR_PHYS_BASE(4)
+ .long MTRR_PHYS_MASK(4)
+ .long MTRR_PHYS_BASE(5)
+ .long MTRR_PHYS_MASK(5)
+ .long MTRR_PHYS_BASE(6)
+ .long MTRR_PHYS_MASK(6)
+ .long MTRR_PHYS_BASE(7)
+ .long MTRR_PHYS_MASK(7)
.long 0x000 /* NULL, end of table */
clear_fixed_var_mtrr_out:
- movl $MTRRphysBase_MSR(0), %ecx
+ movl $MTRR_PHYS_BASE(0), %ecx
xorl %edx, %edx
movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
+ movl $MTRR_PHYS_MASK(0), %ecx
/* This assumes we never access addresses above 2^36 in CAR. */
movl $0x0000000f, %edx
- movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CacheSize - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
/*
* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -125,16 +125,16 @@
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
movl $0x0000000f, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
/* Set the default memory type and enable fixed and variable MTRRs. */
/* TODO: Or also enable fixed MTRRs? Bug in the code? */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx
- movl $(MTRRdefTypeEn), %eax
+ movl $(MTRR_DEF_TYPE_EN), %eax
wrmsr
/* Enable cache. */
@@ -224,24 +224,24 @@
/* Set the default memory type and enable variable MTRRs. */
/* TODO: Or also enable fixed MTRRs? Bug in the code? */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx
- movl $(MTRRdefTypeEn), %eax
+ movl $(MTRR_DEF_TYPE_EN), %eax
wrmsr
/* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */
- movl $MTRRphysBase_MSR(0), %ecx
+ movl $MTRR_PHYS_BASE(0), %ecx
xorl %edx, %edx
movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax
wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
+ movl $MTRR_PHYS_MASK(0), %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff */
- movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
/* Cache XIP_ROM area to speedup coreboot code. */
- movl $MTRRphysBase_MSR(1), %ecx
+ movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
* IMPORTANT: The following calculation _must_ be done at runtime. See
@@ -252,9 +252,9 @@
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
+ movl $MTRR_PHYS_MASK(1), %ecx
xorl %edx, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
/* Enable cache. */
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 3c8450f..c72cf0a 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -179,10 +179,10 @@
#define NUM_FIXED_MTRRS 11
static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
- MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
- MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR,
- MTRRfix4K_D8000_MSR, MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR,
- MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
+ MTRR_FIX_64K_00000, MTRR_FIX_16K_80000, MTRR_FIX_16K_A0000,
+ MTRR_FIX_4K_C0000, MTRR_FIX_4K_C8000, MTRR_FIX_4K_D0000,
+ MTRR_FIX_4K_D8000, MTRR_FIX_4K_E0000, MTRR_FIX_4K_E8000,
+ MTRR_FIX_4K_F0000, MTRR_FIX_4K_F8000,
};
static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
@@ -208,7 +208,7 @@
msr_t msr;
/* Determine number of MTRRs need to be saved. */
- msr = rdmsr(MTRRcap_MSR);
+ msr = rdmsr(MTRR_CAP_MSR);
num_var_mtrrs = msr.lo & 0xff;
/* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE. */
@@ -225,11 +225,11 @@
}
for (i = 0; i < num_var_mtrrs; i++) {
- msr_entry = save_msr(MTRRphysBase_MSR(i), msr_entry);
- msr_entry = save_msr(MTRRphysMask_MSR(i), msr_entry);
+ msr_entry = save_msr(MTRR_PHYS_BASE(i), msr_entry);
+ msr_entry = save_msr(MTRR_PHYS_MASK(i), msr_entry);
}
- msr_entry = save_msr(MTRRdefType_MSR, msr_entry);
+ msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
return msr_count;
}
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 9561d8d..2e31a6e 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -13,10 +13,10 @@
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
- wrmsr(MTRRphysBase_MSR(reg), basem);
- maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+ wrmsr(MTRR_PHYS_BASE(reg), basem);
+ maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRRphysMask_MSR(reg), maskm);
+ wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)
@@ -36,7 +36,7 @@
static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
{
/* Precondition:
- * The cache is not enabled in cr0 nor in MTRRdefType_MSR
+ * The cache is not enabled in cr0 nor in MTRR_DEF_TYPE_MSR
* entry32.inc ensures the cache is not enabled in cr0
*/
msr_t msr;
@@ -65,7 +65,7 @@
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
- wrmsr(MTRRdefType_MSR, msr);
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
@@ -99,7 +99,7 @@
* on both Intel and AMD cpus, at least
* according to the documentation.
*/
- msr = rdmsr(MTRRdefType_MSR);
- return msr.lo & MTRRdefTypeEn;
+ msr = rdmsr(MTRR_DEF_TYPE_MSR);
+ return msr.lo & MTRR_DEF_TYPE_EN;
}
#endif
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 1994a56..072b887 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -64,7 +64,7 @@
{
msr_t msr;
- msr = rdmsr(MTRRcap_MSR);
+ msr = rdmsr(MTRR_CAP_MSR);
total_mtrrs = msr.lo & 0xff;
@@ -81,19 +81,19 @@
{
msr_t msr;
- msr = rdmsr(MTRRdefType_MSR);
- msr.lo |= MTRRdefTypeEn | MTRRdefTypeFixEn;
- wrmsr(MTRRdefType_MSR, msr);
+ msr = rdmsr(MTRR_DEF_TYPE_MSR);
+ msr.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN;
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void enable_var_mtrr(unsigned char deftype)
{
msr_t msr;
- msr = rdmsr(MTRRdefType_MSR);
+ msr = rdmsr(MTRR_DEF_TYPE_MSR);
msr.lo &= ~0xff;
- msr.lo |= MTRRdefTypeEn | deftype;
- wrmsr(MTRRdefType_MSR, msr);
+ msr.lo |= MTRR_DEF_TYPE_EN | deftype;
+ wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
@@ -250,11 +250,11 @@
/* Fixed MTRR descriptors. */
static const struct fixed_mtrr_desc fixed_mtrr_desc[] = {
{ PHYS_TO_RANGE_ADDR(0x000000), PHYS_TO_RANGE_ADDR(0x080000),
- PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRRfix64K_00000_MSR },
+ PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRR_FIX_64K_00000 },
{ PHYS_TO_RANGE_ADDR(0x080000), PHYS_TO_RANGE_ADDR(0x0C0000),
- PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRRfix16K_80000_MSR },
+ PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRR_FIX_16K_80000 },
{ PHYS_TO_RANGE_ADDR(0x0C0000), PHYS_TO_RANGE_ADDR(0x100000),
- PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRRfix4K_C0000_MSR },
+ PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRR_FIX_4K_C0000 },
};
static void calc_fixed_mtrrs(void)
@@ -410,9 +410,9 @@
{
msr_t msr_val;
- msr_val = rdmsr(MTRRphysMask_MSR(index));
- msr_val.lo &= ~MTRRphysMaskValid;
- wrmsr(MTRRphysMask_MSR(index), msr_val);
+ msr_val = rdmsr(MTRR_PHYS_MASK(index));
+ msr_val.lo &= ~MTRR_PHYS_MASK_VALID;
+ wrmsr(MTRR_PHYS_MASK(index), msr_val);
}
static void prep_var_mtrr(struct var_mtrr_state *var_state,
@@ -453,7 +453,7 @@
regs->base.hi = rbase >> 32;
regs->mask.lo = rsize;
- regs->mask.lo |= MTRRphysMaskValid;
+ regs->mask.lo |= MTRR_PHYS_MASK_VALID;
regs->mask.hi = rsize >> 32;
}
@@ -772,8 +772,8 @@
/* Write out the variable MTRRs. */
disable_cache();
for (i = 0; i < sol->num_used; i++) {
- wrmsr(MTRRphysBase_MSR(i), sol->regs[i].base);
- wrmsr(MTRRphysMask_MSR(i), sol->regs[i].mask);
+ wrmsr(MTRR_PHYS_BASE(i), sol->regs[i].base);
+ wrmsr(MTRR_PHYS_MASK(i), sol->regs[i].mask);
}
/* Clear the ones that are unused. */
for (; i < total_mtrrs; i++)
@@ -818,16 +818,16 @@
msr_t msr;
printk(BIOS_DEBUG, "\nMTRR check\n");
- msr = rdmsr(MTRRdefType_MSR);
+ msr = rdmsr(MTRR_DEF_TYPE_MSR);
printk(BIOS_DEBUG, "Fixed MTRRs : ");
- if (msr.lo & MTRRdefTypeFixEn)
+ if (msr.lo & MTRR_DEF_TYPE_FIX_EN)
printk(BIOS_DEBUG, "Enabled\n");
else
printk(BIOS_DEBUG, "Disabled\n");
printk(BIOS_DEBUG, "Variable MTRRs: ");
- if (msr.lo & MTRRdefTypeEn)
+ if (msr.lo & MTRR_DEF_TYPE_EN)
printk(BIOS_DEBUG, "Enabled\n");
else
printk(BIOS_DEBUG, "Disabled\n");