commit | 85d9f470144b8a125b5e439de19138fd5d83c1d5 | [log] [tgz] |
---|---|---|
author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | Mon Nov 08 07:53:37 2021 +0000 |
committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | Wed Nov 17 15:54:10 2021 +0000 |
tree | f7ac1d12e301788b7395ddc19f25a3ed4d99b410 | |
parent | d16a085110d42e28d273e94f96b60ef39c4bb0c2 [diff] |
Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods" This reverts commit 1399442289607acc5203fb12df64e9081b3c3aa4. Reason for revert: Some Cr50 chips with old firmware version (x.y.22) don't support long pulse interrupt command, requiring dynamic GPIO PM to be disabled to intercept short pulse interrupt. Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods to support power gating of GPIO communities from the kernel when dynamic GPIO PM is disabled. BUG=b:204832081 BRANCH=None Test= S0ix works with dynamic PM disabled. Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.