tree dbc388162d51e74300810e79dfe7db4bab883a52
parent b51f54b518bf17a1bfb678d3d14dcf0996d882d2
author Subrata Banik <subrata.banik@intel.com> 1503642250 +0530
committer Aaron Durbin <adurbin@chromium.org> 1503684134 +0000

soc/intel/skylake: Remove ABASE lock down programming

FSP is doing PMC ABASE lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove ABASE Lock down programming
from coreboot.

TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set.

Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>