mb/google/dedede: Support variant specific power limits
With newer dedede design, it's required to config corresponding
psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of
adapter.
BUG=b:281479111
TEST=emerge-dedede coreboot and check correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: I583c930379233322c41027805369f81d02000ee7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75680
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
diff --git a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc
index 64a81f9..2c3f2f6 100644
--- a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc
@@ -4,5 +4,6 @@
romstage-y += memory.c
ramstage-y += gpio.c
+ramstage-y += ramstage.c
smm-y += gpio.c
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
index edb2b07..b258481 100644
--- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
@@ -48,6 +48,30 @@
/* Modify devictree settings during ramstage. */
void variant_devtree_update(void);
+struct psys_config {
+ /*
+ * The efficiency of type-c chargers
+ * For example, 'efficiency = 97' means setting 97% of max power to account for
+ * cable loss and FET Rdson loss in the path from the source.
+ */
+ unsigned int efficiency;
+
+ /* The maximum current maps to the Psys signal */
+ unsigned int psys_imax_ma;
+
+ /* The voltage of barrel jack */
+ unsigned int bj_volts_mv;
+
+ /* The barrel jack power */
+ unsigned int bj_power_w;
+};
+
+/*
+ * Modify Power Limit and PsysPL devictree settings during ramstage.
+ * Note, this function must be called in front of calling variant_update_power_limits.
+ */
+void variant_update_psys_power_limits(const struct psys_config *config);
+
/* Modify LTE devictree settings during ramstage. */
void update_lte_device(struct acpi_gpio *lte_reset_gpio, struct acpi_gpio *lte_enable_gpio);
diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c
new file mode 100644
index 0000000..d43d08f
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi_device.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <drivers/usb/acpi/chip.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <soc/pci_devs.h>
+#include <ec/google/chromeec/ec.h>
+#include <device/pci_ops.h>
+#include <intelblocks/power_limit.h>
+#include <chip.h>
+#include <drivers/intel/dptf/chip.h>
+#include <soc/pci_devs.h>
+
+#define SET_PSYSPL2(e, w) ((e) * (w) / 100)
+#define MICROWATTS_TO_WATTS 1000000
+
+static bool get_sku_index(size_t *intel_idx)
+{
+ uint16_t mch_id = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+ uint8_t tdp = get_cpu_tdp();
+ size_t i = 0;
+
+ if (mch_id != 0xFFFF) {
+ for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) {
+ if (mch_id == cpuid_to_jsl[i].pci_did &&
+ tdp == cpuid_to_jsl[i].cpu_tdp) {
+ *intel_idx = cpuid_to_jsl[i].limits;
+ break;
+ }
+ }
+ }
+
+ if (i == ARRAY_SIZE(cpuid_to_jsl) || mch_id == 0xFFFF) {
+ printk(BIOS_ERR, "Cannot find correct intel sku index.\n");
+ return false;
+ }
+
+ return true;
+}
+
+void variant_update_psys_power_limits(const struct psys_config *config_psys)
+{
+ struct soc_power_limits_config *soc_config;
+ size_t intel_idx = 0;
+ u16 volts_mv, current_ma;
+ enum usb_chg_type type;
+ u32 psys_pl2;
+ config_t *conf;
+ u32 watts;
+ int rv;
+
+ if (!get_sku_index(&intel_idx))
+ return;
+
+ conf = config_of_soc();
+ soc_config = &conf->power_limits_config[intel_idx];
+
+ rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv);
+
+ if (rv == 0 && type == USB_CHG_TYPE_PD) {
+ /* Detected USB-PD. Base on max value of adapter */
+ watts = ((u32)current_ma * volts_mv) / MICROWATTS_TO_WATTS;
+ } else {
+ /* Input type is barrel jack */
+ volts_mv = config_psys->bj_volts_mv;
+ watts = config_psys->bj_power_w;
+ }
+ /* Set psyspl2 to 97% of adapter rating */
+ psys_pl2 = SET_PSYSPL2(config_psys->efficiency, watts);
+
+ /* voltage unit is milliVolts and current is in milliAmps */
+ soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / MICROWATTS_TO_WATTS);
+ conf->PsysPmax = soc_config->psys_pmax;
+
+ soc_config->tdp_psyspl2 = psys_pl2;
+
+ printk(BIOS_INFO, "Overriding PsysPL2 (%uW) Psys_Pmax (%uW)\n",
+ soc_config->tdp_psyspl2,
+ soc_config->psys_pmax);
+}