| commit | 84eb532ec39216c7fcd38ed820ef9b4e22db3085 | [log] [tgz] |
|---|---|---|
| author | Zhuohao Lee <zhuohao@chromium.org> | Fri Jan 21 00:06:06 2022 +0800 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Wed Mar 02 13:10:33 2022 +0000 |
| tree | 3402020a143796b08e3f6f27c9f87659166b5c7b | |
| parent | b8b40964fc1dae62ab237c1a839b66ec105ad860 [diff] |
mb/google/brya/variants: add the smbus addr for dimm1 Align the setting with the adlrvp BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and works correctly in the brask Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/memory.c b/src/mainboard/google/brya/variants/baseboard/brask/memory.c index 2e24110..447328b 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/memory.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/memory.c
@@ -39,5 +39,7 @@ { spd_info->topo = MEM_TOPO_DIMM_MODULE; spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; }