commit 84b9cf4756ff5cda10d4683c5957b6748c3ca377
author Duncan Laurie <dlaurie@chromium.org> Thu Jul 31 10:46:57 2014 -0700
committer Marc Jones <marc.jones@se-eng.com> Fri Mar 27 05:38:37 2015 +0100
tree 77d3ed3211142c2bb56b28087c53a330ca7dcd0f
parent 7b24df41608830bb6368179685e4d92f13a2f505

broadwell: Tweak GFXPAUSE settings based on revision

Changes from 2.1.0 reference code release.

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: I6110a9bdb2973f1a134d8105c37659bf43f61d34
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210607
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ef660ddc6c17a003f06b8995e821c7642c49a56e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibb41cd7369cfc7b9b86b61460650a56415b3d8fb
Reviewed-on: http://review.coreboot.org/8949
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/soc/intel/broadwell/broadwell/systemagent.h

diff --git a/src/soc/intel/broadwell/broadwell/systemagent.h b/src/soc/intel/broadwell/broadwell/systemagent.h
index f95370b..c3b5f94 100644
--- a/src/soc/intel/broadwell/broadwell/systemagent.h
+++ b/src/soc/intel/broadwell/broadwell/systemagent.h
@@ -122,4 +122,7 @@
 /* Data is passed through bits 31:0 of the data register. */
 #define BIOS_MAILBOX_DATA			0x5da0
 
+/* System Agent identification */
+u8 systemagent_revision(void);
+
 #endif

src/soc/intel/broadwell/igd.c

diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 31293e5..53d108d 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -148,8 +148,7 @@
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff),
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010),
 
-	/* GFXPAUSE settings */
-	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00030020),
+	/* GFXPAUSE settings (set based on stepping) */
 
 	/* ECO Settings */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000),
@@ -167,6 +166,9 @@
 	/* Video Frequency Request */
 	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
 
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138158, 0x00000009),
+	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x13815c, 0x0000000d),
+
 	/*
 	 * RC6 Settings
 	 */
@@ -489,6 +491,14 @@
 	/* Early init steps */
 	if (is_broadwell) {
 		reg_script_run_on_dev(dev, broadwell_early_init_script);
+
+		/* Set GFXPAUSE based on stepping */
+		if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
+		    systemagent_revision() <= 9) {
+			gtt_write(0xa000, 0x300ff);
+		} else {
+			gtt_write(0xa000, 0x30020);
+		}
 	} else {
 		reg_script_run_on_dev(dev, haswell_early_init_script);
 	}

src/soc/intel/broadwell/systemagent.c

diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index ac021fb..0488ccb 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -36,6 +36,11 @@
 #include <broadwell/ramstage.h>
 #include <broadwell/systemagent.h>
 
+u8 systemagent_revision(void)
+{
+	return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
+}
+
 static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
 {
 	u32 pciexbar_reg;