tree 4db8e180177d1f5b9768462b8dbd7f7bfd7b1978
parent 313b18abe5415ed31d1dd52344bd27e56278c9e7
author Patrick Rudolph <patrick.rudolph@9elements.com> 1707915061 +0100
committer Lean Sheng Tan <sheng.tan@9elements.com> 1708613869 +0000

soc/intel/xeon_sp: Align resources to 4K

The lower bit of the BAR might be used for something else,
like enable bits, so mask the lower 12 bits and align all
base address to 4K.

Confirmed that all BARs have a minimum alignment of 4K, so that
masking the lower bits doesn't change the reported address.

The alignment of the VTD BARs is:
- VTD_MMCFG_BASE_CSR 64 MiB
- VTD_MMIOL_CSR       1 MiB
- VTD_NCMEM_BASE_CSR 64 MiB
- VTD_TSEG_BASE_CSR   1 MiB
- VTD_BAR_CSR         4 KiB

Change-Id: I9a7b963c0074246616968dd15c147f4916297d59
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>