mb/protectli/vault: Add FW2B and FW4B Braswell based boards support

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I553fd3a89299314a855f055014ca7645100e12e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index e46e0f3..c509c96 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -117,6 +117,10 @@
 
 - [PQ7-M107](portwell/pq7-m107.md)
 
+## Protectli
+
+- [FW2B / FW4B](protectli/fw2b_fw4b.md)
+
 ## Roda
 
 - [RK9 Flash Header](roda/rk9/flash_header.md)
diff --git a/Documentation/mainboard/protectli/fw2b.jpg b/Documentation/mainboard/protectli/fw2b.jpg
new file mode 100644
index 0000000..d6f4105
--- /dev/null
+++ b/Documentation/mainboard/protectli/fw2b.jpg
Binary files differ
diff --git a/Documentation/mainboard/protectli/fw2b_fw4b.md b/Documentation/mainboard/protectli/fw2b_fw4b.md
new file mode 100644
index 0000000..e7d5cbf
--- /dev/null
+++ b/Documentation/mainboard/protectli/fw2b_fw4b.md
@@ -0,0 +1,128 @@
+# Protectli Vault FW2B and FW4B
+
+This page describes how to run coreboot on the [Protectli FW2B] and
+[Protectli FW4B].
+
+
+## Required proprietary blobs
+
+To build a minimal working coreboot image some blobs are required (assuming
+only the BIOS region is being modified).
+
+```eval_rst
++-----------------+---------------------------------+---------------------+
+| Binary file     | Apply                           | Required / Optional |
++=================+=================================+=====================+
+| FSP             | Intel Firmware Support Package  | Required            |
++-----------------+---------------------------------+---------------------+
+| microcode       | CPU microcode                   | Required            |
++-----------------+---------------------------------+---------------------+
+| vgabios         | VGA Option ROM                  | Optional            |
++-----------------+---------------------------------+---------------------+
+```
+
+FSP is automatically added by coreboot build system into the image) from the
+`3rdparty/fsp` submodule.
+
+microcode updates are automatically included into the coreboot image by build
+system from the `3rdparty/intel-microcode` submodule.
+
+VGA Option ROM is not required to boot, but if one needs graphics in pre-OS
+stage, it should be included.
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
+This chip is located on the bottom side of the case (the radiator side). One
+has to remove all screws (in order): 4 top cover screws, 4 side cover screws
+(one side is enough), 4 mainboard screws, 3 CPU screws (under the DIMM). Lift
+up the mainboard and turn around it. The flash chip is near the mainboard edge
+close to the Ethernet Controllers. Use a clip (or solder the wires) to program
+the chip. **Watch out on the voltage, the SPI operates at 1.8V!** Specifically,
+it's a Macronix MX25U6435F (1.8V) - [datasheet][MX25U6435F].
+
+## Known issues
+
+- After flashing with external programmer the board will not boot if flashed
+  the BIOS region only. For some reason it is required to flash whole image
+  along with TXE region.
+- USB 3.0 ports get detected very late in SeaBIOS, it needs huge timeout
+  values in order to get the devices detected.
+
+## Untested
+
+Not all mainboard's peripherals and functions were tested because of lack of
+the cables or not being populated on the board case.
+
+- internal USB 2.0 header
+
+## Working
+
+- USB 3.0 front ports (SeaBIOS and Linux)
+- 4 Ethernet ports (2 Ethernet ports on FW2B)
+- 2 HDMI ports with VGA Option ROM
+- 2 HDMI ports with libgfxinit
+- flashrom
+- PCIe WiFi
+- SATA and mSATA
+- Super I/O serial port 0 (RS232 via front RJ45 connector)
+- SMBus (reading SPD from DIMMs)
+- initialization with Braswell FSP
+- SeaBIOS payload (version rel-1.13.0)
+
+- booting Debian, Ubuntu, FreeBSD
+
+## Not working
+
+- mPCIe debug card connected to mSATA (mSATA slot has LPC signals routed,
+  however for some reason the debug card is not powered)
+
+## Technology
+
+The mainboard has two variants: FW2B and FW4B. They have different Braswell
+SoC. The FW2B replaces 2 out of 4 Ethernet Controllers with 4 USB ports
+connected via [FE1.1 USB 2.0 hub].
+
+- FW2B:
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Celeron J3060                              |
++------------------+--------------------------------------------------+
+| PCH              | Braswell                                         |
++------------------+--------------------------------------------------+
+| Super I/O        | ITE IT8613E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Trusted Execution Engine                   |
++------------------+--------------------------------------------------+
+```
+
+![](fw2b.jpg)
+
+- FW4B:
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Celeron J3160                              |
++------------------+--------------------------------------------------+
+| PCH              | Braswell                                         |
++------------------+--------------------------------------------------+
+| Super I/O        | ITE IT8613E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Trusted Execution Engine                   |
++------------------+--------------------------------------------------+
+```
+
+![](fw4b.jpg)
+
+[Protectli FW2B]: https://protectli.com/vault-2-port/
+[Protectli FW4B]: https://protectli.com/product/fw4b/
+[MX25U6435F]: https://www.macronix.com/Lists/Datasheet/Attachments/7411/MX25U6435F,%201.8V,%2064Mb,%20v1.5.pdf
+[FE1.1 USB 2.0 hub]: https://cdn-shop.adafruit.com/product-files/2991/FE1.1s+Data+Sheet+(Rev.+1.0).pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/protectli/fw4b.jpg b/Documentation/mainboard/protectli/fw4b.jpg
new file mode 100644
index 0000000..98548ea
--- /dev/null
+++ b/Documentation/mainboard/protectli/fw4b.jpg
Binary files differ
diff --git a/src/mainboard/protectli/Kconfig b/src/mainboard/protectli/Kconfig
new file mode 100644
index 0000000..3a1b7a4
--- /dev/null
+++ b/src/mainboard/protectli/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_PROTECTLI
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/protectli/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/protectli/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string "Mainboard Vendor"
+	default "Protectli"
+
+endif # VENDOR_PROTECTLI
diff --git a/src/mainboard/protectli/Kconfig.name b/src/mainboard/protectli/Kconfig.name
new file mode 100644
index 0000000..adc7f05
--- /dev/null
+++ b/src/mainboard/protectli/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_PROTECTLI
+	bool "Protectli"
diff --git a/src/mainboard/protectli/vault_bsw/Kconfig b/src/mainboard/protectli/vault_bsw/Kconfig
new file mode 100644
index 0000000..499bad4
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/Kconfig
@@ -0,0 +1,78 @@
+if BOARD_PROTECTLI_FW2B || BOARD_PROTECTLI_FW4B
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select CACHE_MRC_SETTINGS
+	select DISABLE_HPET
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select PCIEXP_L1_SUB_STATE
+	select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
+	select SOC_INTEL_BRASWELL
+	select SPI_FLASH_MACRONIX
+	select SUPERIO_ITE_IT8613E
+
+config MAINBOARD_DIR
+	string
+	default protectli/vault_bsw
+
+config VARIANT_DIR
+	string
+	default "fw2b" if BOARD_PROTECTLI_FW2B
+	default "fw4b" if BOARD_PROTECTLI_FW4B
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "FW2B" if BOARD_PROTECTLI_FW2B
+	default "FW4B" if BOARD_PROTECTLI_FW4B
+
+config MAINBOARD_VENDOR
+	string
+	default "Protectli"
+
+config DIMM_MAX
+	int
+	default 1
+
+config DIMM_SPD_SIZE
+	int
+	default 256
+
+config MAX_CPUS
+	int
+	default 2 if BOARD_PROTECTLI_FW2B
+	default 4 if BOARD_PROTECTLI_FW4B
+
+config CBFS_SIZE
+	hex
+	default 0x500000
+
+config PXE_ROM_ID
+	string
+	default "8086,1539" if BOARD_PROTECTLI_FW2B
+	default "8086,157b" if BOARD_PROTECTLI_FW4B
+
+if !RUN_FSP_GOP
+config VGA_BIOS_FILE
+	string
+	default "3rdparty/blobs/mainboard/protectli/vault_bsw/vgabios.bin"
+	help
+	  The C0 version of the video bios gets computed from this name
+	  so that they can both be added.  Only the correct one for the
+	  system will be run.
+
+config VGA_BIOS_ID
+	string
+	default "8086,22b0"
+	help
+	  The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
+	  in soc/intel/braswell/Makefile.inc as 8086,22b1
+
+endif #RUN_FSP_GOP
+
+endif # BOARD_PROTECTLI_FW2B
diff --git a/src/mainboard/protectli/vault_bsw/Kconfig.name b/src/mainboard/protectli/vault_bsw/Kconfig.name
new file mode 100644
index 0000000..2255371
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/Kconfig.name
@@ -0,0 +1,5 @@
+config BOARD_PROTECTLI_FW2B
+	bool "FW2B"
+
+config BOARD_PROTECTLI_FW4B
+	bool "FW4B"
diff --git a/src/mainboard/protectli/vault_bsw/Makefile.inc b/src/mainboard/protectli/vault_bsw/Makefile.inc
new file mode 100644
index 0000000..75104bf
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/Makefile.inc
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This file is part of the coreboot project.
+
+bootblock-y += com_init.c
+
+ramstage-y += gpio.c
+ramstage-y += irqroute.c
+ramstage-y += ramstage.c
+ramstage-y += spi_vscc.c
diff --git a/src/mainboard/protectli/vault_bsw/acpi/ec.asl b/src/mainboard/protectli/vault_bsw/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/acpi/ec.asl
diff --git a/src/mainboard/protectli/vault_bsw/acpi/mainboard.asl b/src/mainboard/protectli/vault_bsw/acpi/mainboard.asl
new file mode 100644
index 0000000..06aa41f
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/acpi/mainboard.asl
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Scope (\_SB.GPNC)
+{
+	Method (_AEI, 0, Serialized)  // _AEI: ACPI Event Interrupts
+	{
+		Name (RBUF, ResourceTemplate ()
+		{
+			GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,
+				"\\_SB.GPNC") { BOARD_SCI_GPIO_INDEX }
+		})
+		Return (RBUF)
+	}
+
+	Method (_E0F, 0, NotSerialized)  // _Exx: Edge-Triggered GPE
+	{
+	}
+}
diff --git a/src/mainboard/protectli/vault_bsw/acpi/superio.asl b/src/mainboard/protectli/vault_bsw/acpi/superio.asl
new file mode 100644
index 0000000..940cc23
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/acpi/superio.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Device (COM1) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, One)
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	Name (_CRS, ResourceTemplate ()
+	{
+		FixedIO (0x03F8, 0x08)
+		IRQNoFlags () {4}
+	})
+
+	Name (_PRS, ResourceTemplate ()
+	{
+		StartDependentFn (0, 0) {
+			FixedIO (0x03F8, 0x08)
+			IRQNoFlags () {4}
+		}
+		EndDependentFn ()
+	})
+}
diff --git a/src/mainboard/protectli/vault_bsw/acpi_tables.c b/src/mainboard/protectli/vault_bsw/acpi_tables.c
new file mode 100644
index 0000000..948b562
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/acpi_tables.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <arch/ioapic.h>
+#include <soc/acpi.h>
+#include <string.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset(gnvs, 0, sizeof(*gnvs));
+
+	acpi_init_gnvs(gnvs);
+
+	/* Enable USB ports in S3 */
+	gnvs->s3u0 = 1;
+	gnvs->s3u1 = 1;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0);
+
+	current = acpi_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/src/mainboard/protectli/vault_bsw/board_info.txt b/src/mainboard/protectli/vault_bsw/board_info.txt
new file mode 100644
index 0000000..74144e8
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Protectli
+Board name: FW2B / FW4B
+Category: sbc
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/protectli/vault_bsw/com_init.c b/src/mainboard/protectli/vault_bsw/com_init.c
new file mode 100644
index 0000000..c599039
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/com_init.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8613e/it8613e.h>
+
+#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
+
+void bootblock_mainboard_early_init(void)
+{
+	ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */
+	ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */
+	ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb
new file mode 100644
index 0000000..94c083d
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/devicetree.cb
@@ -0,0 +1,141 @@
+chip soc/intel/braswell
+
+	############################################################
+	# Set the parameters for MemoryInit
+	############################################################
+
+	register "PcdMrcInitTsegSize" = "8"	# SMM Region size in MiB
+
+	register "PcdMrcInitMmioSize" = "0x0800"
+	register "PcdMrcInitSpdAddr1" = "0xa0"
+	register "PcdMrcInitSpdAddr2" = "0xa2"
+	register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB"
+	register "PcdApertureSize" = "2"
+	register "PcdGttSize" = "1"
+	register "PcdDvfsEnable" = "0"
+	register "PcdCaMirrorEn" = "1"
+
+	############################################################
+	# Set the parameters for SiliconInit
+	############################################################
+
+	register "PcdSdcardMode" = "PCH_DISABLED"
+	register "PcdEnableHsuart0" = "0"
+	register "PcdEnableHsuart1" = "0"
+	register "PcdEnableAzalia" = "1"
+	register "PcdEnableXhci" = "1"
+	register "PcdEnableLpe" = "0"
+	register "PcdEnableDma0" = "0"
+	register "PcdEnableDma1" = "0"
+	register "PcdEnableI2C0" = "0"
+	register "PcdEnableI2C1" = "0"
+	register "PcdEnableI2C2" = "0"
+	register "PcdEnableI2C3" = "0"
+	register "PcdEnableI2C4" = "0"
+	register "PcdEnableI2C5" = "0"
+	register "PcdEnableI2C6" = "0"
+	register "PunitPwrConfigDisable" = "1"	# Disable SVID
+	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
+	register "PcdEmmcMode" = "PCH_DISABLED"
+	register "PcdUsb3ClkSsc" = "1"
+	register "PcdDispClkSsc" = "1"
+	register "PcdSataClkSsc" = "1"
+	register "PcdEnableSata" = "1"
+	register "Usb2Port0PerPortPeTxiSet" = "7"
+	register "Usb2Port0PerPortTxiSet" = "6"
+	register "Usb2Port0IUsbTxEmphasisEn" = "3"
+	register "Usb2Port0PerPortTxPeHalf" = "1"
+	register "Usb2Port1PerPortPeTxiSet" = "7"
+	register "Usb2Port1PerPortTxiSet" = "6"
+	register "Usb2Port1IUsbTxEmphasisEn" = "3"
+	register "Usb2Port1PerPortTxPeHalf" = "1"
+	register "Usb2Port2PerPortPeTxiSet" = "7"
+	register "Usb2Port2PerPortTxiSet" = "6"
+	register "Usb2Port2IUsbTxEmphasisEn" = "3"
+	register "Usb2Port2PerPortTxPeHalf" = "1"
+	register "Usb2Port3PerPortPeTxiSet" = "7"
+	register "Usb2Port3PerPortTxiSet" = "6"
+	register "Usb2Port3IUsbTxEmphasisEn" = "3"
+	register "Usb2Port3PerPortTxPeHalf" = "1"
+	register "Usb2Port4PerPortPeTxiSet" = "7"
+	register "Usb2Port4PerPortTxiSet" = "6"
+	register "Usb2Port4IUsbTxEmphasisEn" = "3"
+	register "Usb2Port4PerPortTxPeHalf" = "1"
+	register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
+	register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
+	register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
+	register "PcdSataInterfaceSpeed" = "3"
+	register "PcdPchSsicEnable" = "1"
+	register "PcdRtcLock" = "0"	# Disable RTC access locking to NVRAM
+	register "PMIC_I2CBus" = "0"
+	register "ISPEnable" = "0"		# Disable IUNIT
+	register "ISPPciDevConfig" = "3"
+	register "PcdSdDetectChk" = "0" # Disable SD card detect
+	register "DptfDisable" = "1"
+
+	# Enable devices in PCI mode
+	register "lpss_acpi_mode" = "0"
+	register "emmc_acpi_mode" = "0"
+	register "sd_acpi_mode" = "0"
+	register "lpe_acpi_mode" = "0"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable SERIRQ continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end	# 8086 2280 - SoC transaction router
+		device pci 02.0 on  end	# 8086 22b0/22b1 - B1/C0 stepping GFX
+		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
+		device pci 0b.0 off end	# 8086 22dc - PUNIT/DPTF
+		device pci 10.0 off end	# 8086 2294 - MMC Port
+		device pci 12.0 off end	# 8086 2296 - SD Port
+		device pci 13.0 on  end	# 8086 22a3 - Sata controller
+		device pci 14.0 on  end	# 8086 22b5 - USB XHCI
+		device pci 18.0 off end	# 8086 22c0 - SIO - DMA
+		device pci 18.1 off end	# 8086 22c1 -   I2C Port 1
+		device pci 18.2 off end	# 8086 22c2 -   I2C Port 2
+		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
+		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
+		device pci 18.5 off end	# 8086 22c5 -   I2C Port 5
+		device pci 18.6 off end	# 8086 22c6 -   I2C Port 6
+		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
+		device pci 1a.0 on  end	# 8086 2298 - Trusted Execution Engine
+		device pci 1b.0 on  end	# 8086 2284 - HD Audio
+		device pci 1c.0 on  end	# 8086 22c8 - PCIe Root Port 1
+		device pci 1c.1 on  end	# 8086 22ca - PCIe Root Port 2
+		device pci 1c.2 on  end	# 8086 22cc - PCIe Root Port 3
+		device pci 1c.3 on	# 8086 22ce - PCIe Root Port 4
+			smbios_slot_desc
+				"SlotTypePciExpressMini52pinWithoutBSKO"
+				"SlotLengthShort" "WIFI" "SlotDataBusWidth1X"
+		end
+		device pci 1e.0 off end	# 8086 2286 - SIO - DMA
+		device pci 1e.3 off end	# 8086 228a -   HSUART 1
+		device pci 1e.4 off end	# 8086 228c -   HSUART 2
+		device pci 1f.0 on	# 8086 229c - LPC bridge
+			chip superio/ite/it8613e
+				device pnp 2e.0 off end
+				device pnp 2e.1 on	# COM 1
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+				end
+				device pnp 2e.4 off end # Environment Controller
+				device pnp 2e.5 off end # Keyboard
+				device pnp 2e.6 off end # Mouse
+				device pnp 2e.7 off end # GPIO
+				device pnp 2e.a off end # CIR
+			end
+		end
+		device pci 1f.3 on end	# 8086 2292 - SMBus 0
+	end
+end
diff --git a/src/mainboard/protectli/vault_bsw/dsdt.asl b/src/mainboard/protectli/vault_bsw/dsdt.asl
new file mode 100644
index 0000000..34f93fa
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/dsdt.asl
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM revision */
+)
+{
+	#include "onboard.h"
+
+	#include <acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <acpi/southcluster.asl>
+
+		Device (RP03)
+		{
+			Name (_ADR, 0x001C0002)  // _ADR: Address
+			OperationRegion(RPXX, PCI_Config, 0x00, 0x10)
+		}
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/protectli/vault_bsw/fadt.c b/src/mainboard/protectli/vault_bsw/fadt.c
new file mode 100644
index 0000000..a84e063
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/fadt.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <soc/acpi.h>
+#include <string.h>
+#include <version.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = get_acpi_table_revision(FADT);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = asl_revision;
+
+	fadt->firmware_ctrl = (unsigned long)facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	acpi_fill_in_fadt(fadt);
+
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
+
+	header->checksum = acpi_checksum((void *)fadt, header->length);
+}
diff --git a/src/mainboard/protectli/vault_bsw/gpio.c b/src/mainboard/protectli/vault_bsw/gpio.c
new file mode 100644
index 0000000..741d51e
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/gpio.c
@@ -0,0 +1,238 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <soc/gpio.h>
+
+/* South East Community */
+static const struct soc_gpio_map gpse_gpio_map[] = {
+	GPIO_NC,			/* 00 MF_PLT_CLK0 */
+	GPIO_NC,			/* 01 PWM1 */
+	GPIO_NC,			/* 02 MF_PLT_CLK1 */
+	GPIO_NC,			/* 03 MF_PLT_CLK4 */
+	GPIO_NC,			/* 04 MF_PLT_CLK3 */
+	GPIO_NC,			/* 05 PWM0*/
+	GPIO_NC,			/* 06 MF_PLT_CLK5 */
+	GPIO_NC,			/* 07 MF_PLT_CLK2 */
+	GPIO_NC,			/* 15 SDMMC2_D3_CD_B */
+	GPIO_NC,			/* 16 SDMMC1_CLK */
+	GPIO_NC,			/* 17 SDMMC1_D0 */
+	GPIO_NC,			/* 18 SDMMC2_D1 */
+	GPIO_NC,			/* 19 SDMMC2_CLK */
+	GPIO_NC,			/* 20 SDMMC1_D2 */
+	GPIO_NC,			/* 21 SDMMC2_D2 */
+	GPIO_NC,			/* 22 SDMMC2_CMD  */
+	GPIO_NC,			/* 23 SDMMC1_CMD */
+	GPIO_NC,			/* 24 SDMMC1_D1 */
+	GPIO_NC,			/* 25 SDMMC2_D0 */
+	GPIO_NC,			/* 26 SDMMC1_D3_CD_B */
+	GPIO_NC,			/* 30 SDMMC3_D1 */
+	GPIO_NC,			/* 31 SDMMC3_CLK */
+	GPIO_NC,			/* 32 SDMMC3_D3 */
+	GPIO_NC,			/* 33 SDMMC3_D2 */
+	GPIO_NC,			/* 34 SDMMC3_CMD */
+	GPIO_NC,			/* 35 SDMMC3_D0 */
+	NATIVE_PU20K(1),		/* 45 MF_LPC_AD2 */
+	NATIVE_PU20K(1),		/* 46 LPC_CLKRUNB */
+	NATIVE_PU20K(1),		/* 47 MF_LPC_AD0 */
+	Native_M1,			/* 48 LPC_FRAMEB */
+	Native_M1,			/* 49 MF_LPC_CLKOUT1 */
+	NATIVE_PU20K(1),		/* 50 MF_LPC_AD3 */
+	Native_M1,			/* 51 MF_LPC_CLKOUT0 */
+	NATIVE_PU20K(1),		/* 52 MF_LPC_AD1 */
+	GPIO_NC,			/* 60 SPI1_MISO */
+	GPIO_NC,			/* 61 SPI1_CS0_B */
+	GPIO_NC,			/* 62 SPI1_CLK */
+	GPIO_NC,			/* 63 MMC1_D6 */
+	GPIO_NC,			/* 64 SPI1_MOSI */
+	GPIO_NC,			/* 65 MMC1_D5 */
+	GPIO_NC,			/* 66 SPI1_CS1_B */
+	GPIO_NC,			/* 67 MMC1_D4_SD_WE */
+	GPIO_NC,			/* 68 MMC1_D7 */
+	GPIO_NC,			/* 69 MMC1_RCLK */
+	Native_M1,			/* 75 USB_OC1_B */
+	Native_M1,			/* 76 PMU_RESETBUTTON_B */
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
+	/* 77 GPIO_ALERT   */
+	GPIO_NC,			/* 78 SDMMC3_PWR_EN_B */
+	NATIVE_PU20K(1),		/* 79 ILB_SERIRQ */
+	NATIVE_PU20K(1),		/* 80 USB_OC0_B */
+	GPIO_NC,			/* 81 SDMMC3_CD_B */
+	Native_M1,			/* 82 SPKR */
+	Native_M1,			/* 83 SUSPWRDNACK */
+	SPARE_PIN,			/* 84 SDMMC1_RCLK */
+	GPIO_NC,			/* 85 SDMMC3_1P8_EN */
+	GPIO_END
+};
+
+/* South West Community */
+static const struct soc_gpio_map  gpsw_gpio_map[] = {
+	NATIVE_PU20K(1),		/* 00 FST_SPI_D2 */
+	NATIVE_PU20K(1),		/* 01 FST_SPI_D0 */
+	NATIVE_PU20K(1),		/* 02 FST_SPI_CLK */
+	NATIVE_PU20K(1),		/* 03 FST_SPI_D3 */
+	GPO_FUNC(P_20K_H, 1),		/* 04 FST_SPI_CS1_B */
+	NATIVE_PU20K(1),		/* 05 FST_SPI_D1 */
+	NATIVE_PU20K(1),		/* 06 FST_SPI_CS0_B */
+	GPO_FUNC(P_20K_H, 1),		/* 07 FST_SPI_CS2_B */
+	GPIO_NC,			/* 15 UART1_RTS_B */
+	GPIO_NC,			/* 16 UART1_RXD */
+	GPIO_NC,			/* 17 UART2_RXD */
+	GPIO_NC,			/* 18 UART1_CTS_B */
+	GPIO_NC,			/* 19 UART2_RTS_B */
+	GPIO_NC,			/* 20 UART1_TXD */
+	GPIO_NC,			/* 21 UART2_TXD */
+	GPIO_NC,			/* 22 UART2_CTS_B */
+	NATIVE_PD20K(2),		/* 30 MF_HDA_CLK */
+	NATIVE_PD20K(2),		/* 31 GPIO_SW31/MF_HDA_RSTB */
+	NATIVE_PD20K(2),		/* 32 GPIO_SW32/MF_HDA_SDI0 */
+	NATIVE_PD20K(2),		/* 33 MF_HDA_SDO */
+	GPO_FUNC(P_20K_L, 1),		/* 34 MF_HDA_DOCKRSTB */
+	NATIVE_PD20K(2),		/* 35 MF_HDA_SYNC */
+	NATIVE_PD20K(2),		/* 36 GPIO_SW36/MF_HDA_SDI1 */
+	GPIO_INPUT_PD_20K,		/* 37 MF_HDA_DOCKENB */
+	GPIO_NC,			/* 45 I2C5_SDA */
+	GPIO_NC,			/* 46 I2C4_SDA */
+	GPIO_NC,			/* 47 I2C6_SDA */
+	GPIO_NC,			/* 48 I2C5_SCL */
+	GPIO_NC,			/* 49 I2C_NFC_SDA */
+	GPIO_NC,			/* 50 I2C4_SCL */
+	GPIO_NC,			/* 51 I2C6_SCL */
+	GPIO_NC,			/* 52 I2C_NFC_SCL */
+	GPIO_NC,			/* 60 I2C1_SDA */
+	GPIO_NC,			/* 61 I2C0_SDA */
+	GPIO_NC,			/* 62 I2C2_SDA */
+	GPIO_NC,			/* 63 I2C1_SCL */
+	GPIO_NC,			/* 64 I2C3_SDA */
+	GPIO_NC,			/* 65 I2C0_SCL */
+	GPIO_NC,			/* 66 I2C2_SCL */
+	GPIO_NC,			/* 67 I2C3_SCL */
+	GPIO_NC,			/* 75 SATA_GP0 */
+	GPIO_NC,			/* 76 SATA_GP1 */
+	Native_M1,			/* 77 SATA_LEDN */
+	GPIO_NC,			/* 78 SATA_GP2 */
+	NATIVE_PU20K(1),		/* 79 MF_SMB_ALERTB */
+	GPIO_NC,			/* 80 SATA_GP3 */
+	NATIVE_PU20K(1),		/* 81 MF_SMB_CLK */
+	NATIVE_PU20K(1),		/* 82 MF_SMB_DATA */
+	GPIO_NC,			/* 90 PCIE_CLKREQ0B */
+	GPIO_NC,			/* 91 PCIE_CLKREQ1B */
+	GPIO_NC,			/* 92 GP_SSP_2_CLK */
+	GPIO_NC,			/* 93 PCIE_CLKREQ2B */
+	GPIO_NC,			/* 94 GP_SSP_2_RXD */
+	GPIO_NC,			/* 95 PCIE_CLKREQ3B */
+	GPIO_NC,			/* 96 GP_SSP_2_FS */
+	GPIO_NC,			/* 97 GP_SSP_2_TXD */
+	GPIO_END
+};
+
+/* North Community */
+static const struct soc_gpio_map  gpn_gpio_map[] = {
+	GPIO_NC,			/* 00 GPIO_DFX0 */
+	GPIO_NC,			/* 01 GPIO_DFX3 */
+	GPIO_NC,			/* 02 GPIO_DFX7 */
+	GPIO_NC,			/* 03 GPIO_DFX1 */
+	GPIO_NC,			/* 04 GPIO_DFX5 */
+	GPIO_NC,			/* 05 GPIO_DFX4 */
+	GPIO_NC,			/* 06 GPIO_DFX8 */
+	GPIO_NC,			/* 07 GPIO_DFX2 */
+	GPIO_NC,			/* 08 GPIO_DFX6 */
+	GPI(trig_edge_low, L8, P_20K_L, non_maskable, en_edge_rx_data,
+	    UNMASK_WAKE, SCI),		/* 15 GPIO_SUS0 */
+	GPO_FUNC(P_20K_L, 1),		/* 16 SEC_GPIO_SUS10 */
+	NATIVE_PD20K(1),		/* 17 GPIO_SUS3 */
+	GPI(trig_edge_low, L15, P_20K_H, non_maskable, en_edge_rx_data, NA,
+	    SMI),			/* 18 GPIO_SUS7 */
+	NATIVE_PD20K(1),		/* 19 GPIO_SUS1 */
+	GPIO_INPUT_PU_20K,		/* 20 GPIO_SUS5 */
+	GPI(trig_edge_high, L2, P_20K_L, non_maskable, en_edge_rx_data, NA,
+	    NA),			/* 21 SEC_GPIO_SUS11 */
+	NATIVE_PU20K(1),		/* 22 GPIO_SUS4 */
+	GPI(trig_level_high, L3, P_20K_H, non_maskable, en_rx_data, NA, NA),
+					/* 23 SEC_GPIO_SUS8 */
+	NATIVE_PU20K(1),		/* 24 GPIO_SUS2 */
+	GPI(trig_edge_low, L14, P_20K_H, non_maskable, en_edge_rx_data, NA,
+	    SCI),			/* 25 GPIO_SUS6 */
+	Native_M1,			/* 26 CX_PREQ_B */
+	GPIO_INPUT_PD_20K,		/* 27 SEC_GPIO_SUS9 */
+	Native_M1,			/* 30 TRST_B */
+	Native_M1,			/* 31 TCK */
+	GPIO_SKIP,			/* 32 PROCHOT_B */
+	GPIO_SKIP,			/* 33 SVID0_DATA */
+	Native_M1,			/* 34 TMS */
+	GPIO_NC,			/* 35 CX_PRDY_B_2 */
+	GPIO_NC,			/* 36 TDO_2 */
+	Native_M1,			/* 37 CX_PRDY_B */
+	GPIO_SKIP,			/* 38 SVID0_ALERT_B */
+	Native_M1,			/* 39 TDO */
+	GPIO_SKIP,			/* 40 SVID0_CLK */
+	Native_M1,			/* 41 TDI */
+	GPIO_NC,			/* 45 GP_CAMERASB05 */
+	GPIO_NC,			/* 46 GP_CAMERASB02 */
+	GPIO_NC,			/* 47 GP_CAMERASB08 */
+	GPIO_NC,			/* 48 GP_CAMERASB00 */
+	GPIO_NC,			/* 49 GP_CAMERASBO6 */
+	GPIO_NC,			/* 50 GP_CAMERASB10 */
+	GPIO_NC,			/* 51 GP_CAMERASB03 */
+	GPIO_NC,			/* 52 GP_CAMERASB09 */
+	GPIO_NC,			/* 53 GP_CAMERASB01 */
+	GPIO_NC,			/* 54 GP_CAMERASB07 */
+	GPIO_NC,			/* 55 GP_CAMERASB11 */
+	GPIO_NC,			/* 56 GP_CAMERASB04 */
+	GPIO_NC,			/* 60 PANEL0_BKLTEN */
+	NATIVE_TX_RX_EN,		/* 61 HV_DDI0_HPD */
+	NATIVE_PU1K_M1,			/* 62 HV_DDI2_DDC_SDA */
+	GPIO_NC,			/* 63 PANEL1_BKLTCTL */
+	GPIO_NC,			/* 64 HV_DDI1_HPD */
+	GPIO_NC,			/* 65 PANEL0_BKLTCTL */
+	NATIVE_PU1K_M1,			/* 66 HV_DDI0_DDC_SDA */
+	NATIVE_PU1K_M1,			/* 67 HV_DDI2_DDC_SCL */
+	NATIVE_TX_RX_EN,		/* 68 HV_DDI2_HPD */
+	GPIO_NC,			/* 69 PANEL1_VDDEN */
+	GPIO_NC,			/* 70 PANEL1_BKLTEN */
+	NATIVE_PU1K_M1,			/* 71 HV_DDI0_DDC_SCL */
+	GPIO_NC,			/* 72 PANEL0_VDDEN */
+	GPIO_END
+};
+
+/* East Community */
+static const struct soc_gpio_map  gpe_gpio_map[] = {
+	NATIVE_PU20K(1),		/* 00 PMU_SLP_S3_B */
+	NATIVE_PU20K(1),		/* 01 PMU_BATLOW_B */
+	NATIVE_PU20K(1),		/* 02 SUS_STAT_B */
+	NATIVE_PU20K(1),		/* 03 PMU_SLP_S0IX_B */
+	NATIVE_PD20K(1),		/* 04 PMU_AC_PRESENT */
+	NATIVE_PU20K(1),		/* 05 PMU_PLTRST_B */
+	NATIVE_PD20K(1),		/* 06 PMU_SUSCLK */
+	NATIVE_PU20K(1),		/* 07 PMU_SLP_LAN_B */
+	NATIVE_PU20K(1),		/* 08 PMU_PWRBTN_B */
+	NATIVE_PU20K(1),		/* 09 PMU_SLP_S4_B */
+	NATIVE_FUNC_TX_RX(en_rx_data << 2, 1, P_1K_H, NA), /* 10 PMU_WAKE_B */
+	GPIO_NC,			/* 11 PMU_WAKE_LAN_B */
+	GPIO_NC,			/* 15 MF_GPIO_3 */
+	GPIO_NC,			/* 16 MF_GPIO_7 */
+	GPIO_NC,			/* 17 MF_I2C1_SCL */
+	GPIO_NC,			/* 18 MF_GPIO_1 */
+	GPIO_NC,			/* 19 MF_GPIO_5 */
+	GPIO_NC,			/* 20 MF_GPIO_9 */
+	GPIO_NC,			/* 21 MF_GPIO_0 */
+	GPIO_NC,			/* 22 MF_GPIO_4 */
+	GPIO_NC,			/* 23 MF_GPIO_8 */
+	GPIO_NC,			/* 24 MF_GPIO_2 */
+	GPIO_NC,			/* 25 MF_GPIO_6 */
+	GPIO_NC,			/* 26 MF_I2C1_SDA */
+	GPIO_END
+};
+
+static struct soc_gpio_config gpio_config = {
+	/* BSW */
+	.north = gpn_gpio_map,
+	.southeast = gpse_gpio_map,
+	.southwest  = gpsw_gpio_map,
+	.east = gpe_gpio_map
+};
+
+struct soc_gpio_config *mainboard_get_gpios(void)
+{
+
+	return &gpio_config;
+}
diff --git a/src/mainboard/protectli/vault_bsw/irqroute.c b/src/mainboard/protectli/vault_bsw/irqroute.c
new file mode 100644
index 0000000..79bce75
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/irqroute.c
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/protectli/vault_bsw/irqroute.h b/src/mainboard/protectli/vault_bsw/irqroute.h
new file mode 100644
index 0000000..5c2e34d
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/irqroute.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,    A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV,   D, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,   E, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,   B, A, D, C), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,    F, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,    G, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,   A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,   D, B, C, A), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,    A, C, A, A)
+
+#define PIRQ_PIC_ROUTES \
+	PIRQ_PIC(A, 11), \
+	PIRQ_PIC(B, 5), \
+	PIRQ_PIC(C, 5), \
+	PIRQ_PIC(D, 11), \
+	PIRQ_PIC(E, 11), \
+	PIRQ_PIC(F, 5), \
+	PIRQ_PIC(G, 11), \
+	PIRQ_PIC(H, 11)
diff --git a/src/mainboard/protectli/vault_bsw/mainboard.c b/src/mainboard/protectli/vault_bsw/mainboard.c
new file mode 100644
index 0000000..1fd8919
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <arch/mmio.h>
+#include <device/device.h>
+#include <soc/iomap.h>
+
+#define BIOS_CONTROL_REG	0xFC
+#define   BIOS_CONTROL_WPD	(1 << 0)
+
+static void mainboard_enable(struct device *dev)
+{
+	volatile void *addr = (void *)(SPI_BASE_ADDRESS + BIOS_CONTROL_REG);
+
+	/* Set Bios Write Protect Disable bit to allow saving MRC cache */
+	write8(addr, read8(addr) | BIOS_CONTROL_WPD);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/protectli/vault_bsw/onboard.h b/src/mainboard/protectli/vault_bsw/onboard.h
new file mode 100644
index 0000000..fcdb3a7
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/onboard.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+/*
+ * Calculation of gpio based irq.
+ * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
+ * Max direct irq (MAX_DIRECT_IRQ) is 114.
+ * Size of gpio banks are
+ * GPSW_SIZE = 98
+ * GPNC_SIZE = 73
+ * GPEC_SIZE = 27
+ * GPSE_SIZE = 86
+ */
+
+
+/* Audio: Gpio index in SW bank */
+#define JACK_DETECT_GPIO_INDEX		77
+
+/* SCI: Gpio index in N bank */
+#define BOARD_SCI_GPIO_INDEX		15
+
+#define SDCARD_CD			81
+
+#define AUDIO_CODEC_HID			"10EC5670"
+#define AUDIO_CODEC_CID			"10EC5670"
+#define AUDIO_CODEC_DDN			"RTEK Codec Controller "
+#define AUDIO_CODEC_I2C_ADDR		0x1C
+
+#define BCRD2_PMIC_I2C_BUS		0x01
+
+#endif
diff --git a/src/mainboard/protectli/vault_bsw/ramstage.c b/src/mainboard/protectli/vault_bsw/ramstage.c
new file mode 100644
index 0000000..6320ca7
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/ramstage.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+{
+	params->PcdTurboMode = 1;
+}
diff --git a/src/mainboard/protectli/vault_bsw/romstage.c b/src/mainboard/protectli/vault_bsw/romstage.c
new file mode 100644
index 0000000..37a75dc
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/romstage.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <device/pci_ops.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8613e/it8613e.h>
+
+#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1)
+
+void mainboard_after_memory_init(void)
+{
+	/*
+	 * FSP enables internal UART. Disable it and reenable Super I/O UART to
+	 * prevent loss of debug information on serial.
+	 */
+	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0);
+	ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_memory_init_params(struct romstage_params *params,
+				  MEMORY_INIT_UPD *memory_params)
+{
+	/*
+	 * Set SPD and memory configuration:
+	 * Memory type: 0=DimmInstalled,
+	 *              1=SolderDownMemory,
+	 *              2=DimmDisabled
+	 */
+	memory_params->PcdMemChannel0Config = 0;
+	memory_params->PcdMemChannel1Config = 2;
+}
diff --git a/src/mainboard/protectli/vault_bsw/spi_vscc.c b/src/mainboard/protectli/vault_bsw/spi_vscc.c
new file mode 100644
index 0000000..529a78eb
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/spi_vscc.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <soc/spi.h>
+#include <string.h>
+
+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
+
+static const struct vscc_config spi_config = {
+	.lvscc =  SPI_VSCC,
+	.uvscc =  SPI_VSCC,
+};
+
+int mainboard_get_spi_vscc_config(struct vscc_config *cfg)
+{
+	memcpy(cfg, &spi_config, sizeof(*cfg));
+	return 0;
+}
diff --git a/src/mainboard/protectli/vault_bsw/variants/fw2b/overridetree.cb b/src/mainboard/protectli/vault_bsw/variants/fw2b/overridetree.cb
new file mode 100644
index 0000000..2cccd85
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/variants/fw2b/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/braswell
+
+	device domain 0 on
+		device pci 1c.2 off end	# 8086 22cc - PCIe Root Port 3
+	end
+end
diff --git a/src/mainboard/protectli/vault_bsw/variants/fw4b/overridetree.cb b/src/mainboard/protectli/vault_bsw/variants/fw4b/overridetree.cb
new file mode 100644
index 0000000..a9c0199
--- /dev/null
+++ b/src/mainboard/protectli/vault_bsw/variants/fw4b/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/braswell
+
+	device domain 0 on
+		device pci 1c.2 on end	# 8086 22cc - PCIe Root Port 3
+	end
+end