tree ebcee8a625ed81f6beffe9a0324c713d6a20b9a6
parent 6b2b8355b321301f39335246afc0db71496961c3
author Arthur Heymans <arthur@aheymans.xyz> 1675102174 +0100
committer Arthur Heymans <arthur@aheymans.xyz> 1677142418 +0000

soc/intel: Use common codeflow for MP init

This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*:
Remove lapic from devicetree).

Alderlake cpu code was linked in romstage but unused so drop it.

Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>