soc/intel: Use common codeflow for MP init
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*:
Remove lapic from devicetree).
Alderlake cpu code was linked in romstage but unused so drop it.
Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 21d6e17..9d94d8b 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -49,7 +49,7 @@
static struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
- .init = cpx_init_cpus,
+ .init = mp_cpu_bus_init,
.acpi_fill_ssdt = generate_cpu_entries,
};
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 0e95131..fefb900 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -211,7 +211,7 @@
.post_mp_init = post_mp_init,
};
-void cpx_init_cpus(struct device *dev)
+void mp_init_cpus(struct bus *bus)
{
microcode_patch = intel_microcode_find();
@@ -221,13 +221,13 @@
intel_microcode_load_unlocked(microcode_patch);
/* TODO: Handle mp_init_with_smm failure? */
- mp_init_with_smm(dev->link_list, &mp_ops);
+ mp_init_with_smm(bus, &mp_ops);
/*
* chip_config is used in cpu device callback. Other than cpu 0,
* rest of the CPU devices do not have chip_info updated.
*/
- chip_config = dev->chip_info;
+ chip_config = bus->dev->chip_info;
/* update numa domain for all cpu devices */
xeonsp_init_cpu_config();