nb/intel/sandybridge: Factor out timing tables
The timing tables for Sandy Bridge are a subset of Ivy Bridge's tables.
Move the latter to a common place, and use it for both generations.
Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, both work.
Change-Id: Id14227febf4eebb8a2b4d2d4f37759d0f42648c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39735
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/raminit_tables.c b/src/northbridge/intel/sandybridge/raminit_tables.c
index 1ecba1b..67dbd2b 100644
--- a/src/northbridge/intel/sandybridge/raminit_tables.c
+++ b/src/northbridge/intel/sandybridge/raminit_tables.c
@@ -3,6 +3,111 @@
#include "raminit_tables.h"
+const u32 frq_refi_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */
+ 3120, 4160, 5200, 6240, 7280, 8320, 9360, 10400,
+ },
+ { /* 100 MHz */
+ /* FRQ: 7, 8, 9, 10, 11, 12, N/A, N/A, */
+ 5460, 6240, 7020, 7800, 8580, 9360, 0, 0,
+ },
+};
+
+const u8 frq_xs_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */
+ 4, 6, 7, 8, 10, 11, 12, 14,
+ },
+ { /* 100 MHz */
+ /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */
+ 7, 8, 9, 10, 11, 12, 0, 0,
+ },
+};
+
+const u8 frq_mod_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */
+ 12, 12, 12, 12, 15, 16, 18, 20,
+ },
+ { /* 100 MHz */
+ /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */
+ 12, 12, 14, 15, 17, 18, 0, 0,
+ },
+};
+
+const u8 frq_wlo_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */
+ 4, 5, 6, 6, 8, 8, 9, 10,
+ },
+ { /* 100 MHz */
+ /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */
+ 6, 6, 7, 8, 9, 9, 0, 0,
+ },
+};
+
+const u8 frq_cke_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */
+ 3, 3, 4, 4, 5, 6, 6, 7,
+ },
+ { /* 100 MHz */
+ /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */
+ 4, 4, 5, 5, 6, 6, 0, 0,
+ },
+};
+
+const u8 frq_xpdll_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */
+ 10, 13, 16, 20, 23, 26, 29, 32,
+ },
+ { /* 100 MHz */
+ /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */
+ 17, 20, 22, 24, 27, 32, 0, 0,
+ },
+};
+
+const u8 frq_xp_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */
+ 3, 4, 4, 5, 6, 7, 8, 8,
+ },
+ { /* 100 MHz */
+ /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */
+ 5, 5, 6, 6, 7, 8, 0, 0,
+ },
+};
+
+const u8 frq_aonpd_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 3, 4, 5, 6, 7, 8, 9, 10, */
+ 4, 5, 6, 8, 8, 10, 11, 12,
+ },
+ { /* 100 MHz */
+ /* FRQ: 7, 8, 9, 10, 11, 12, NA, NA, */
+ 6, 8, 8, 9, 10, 11, 0, 0,
+ },
+};
+
+const u32 frq_comp2_map[2][8] = {
+ { /* 133 MHz */
+ /* FRQ: 7, 8, 9, 10, */
+ 0x0CA8C264, 0x0C6671E4, 0x0C6671E4, 0x0C446964,
+
+ /* FRQ: 11, 12, N/A, N/A, */
+ 0x0C235924, 0x0C235924, 0, 0,
+ },
+ { /* 100 MHz */
+ /* FRQ: 3, 4, 5, 6, */
+ 0x0D6FF5E4, 0x0CEBDB64, 0x0CA8C264, 0x0C6671E4,
+
+ /* FRQ: 7, 8, 9, 10, */
+ 0x0C446964, 0x0C235924, 0x0C235924, 0x0C235924,
+ },
+};
+
const u32 pattern[32][16] = {
{0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
0x00000000, 0x00000000, 0xffffffff, 0xffffffff,