soc/intel/xeon_sp/spr: Add RMT config
This commit adds a configuration option to enable RMT in the coreboot
build for the Intel Xeon SP SPR platform.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 308ec2d..f666ab5 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -182,4 +182,10 @@
ASPM. This option is intended for debugging and validation and
should normally be disabled.
+config ENABLE_RMT
+ bool "Enable RMT"
+ default n
+ help
+ Enable Rank Margining Tool. This option is intended for debugging and
+ validation and should normally be disabled.
endif
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 8f4e98e..fef4d94 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -217,6 +217,13 @@
mupd->FspmConfig.KtiLinkL1En = 0;
mupd->FspmConfig.KtiLinkL0pEn = 0;
}
+
+ if (CONFIG(ENABLE_RMT)) {
+ printk(BIOS_INFO, "RMT Enabled.\n");
+ mupd->FspmConfig.EnableRMT = 0x1;
+ /* Set FSP debug message to Max for RMT logs */
+ mupd->FspmConfig.serialDebugMsgLvl = 0x3;
+ }
}
static uint8_t get_error_correction_type(const uint8_t RasModesEnabled)