intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup
Adapt implementation from skylake to prepare for removal of
HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE.
With this change, CBMEM region is set early-on as WRBACK
with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 4f60034..14f841c 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -14,6 +14,7 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
#include <program_loading.h>
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
@@ -41,10 +42,7 @@
}
/* Get the stack to use after cache-as-ram is torn down. */
- if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
- romstage_stack_after_car = (void*)CONFIG_RAMTOP;
- else
- romstage_stack_after_car = setup_stack_and_mtrrs();
+ romstage_stack_after_car = setup_stack_and_mtrrs();
return romstage_stack_after_car;
}
@@ -54,3 +52,26 @@
/* Load the ramstage. */
run_ramstage();
}
+
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
+void *setup_stack_and_mtrrs(void)
+{
+ struct postcar_frame pcf;
+
+ postcar_frame_init_lowmem(&pcf);
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Save the number of MTRRs to setup. Return the stack location
+ * pointing to the number of MTRRs.
+ */
+ return postcar_commit_mtrrs(&pcf);
+}
+#endif /* CONFIG_LATE_CBMEM_INIT */