mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also
initializing it (if ISH is enabled) to be NF2 (ISH_GP4). Also took
the liberty of alphabetizing all the ISH GPIOs to they're easier to
search through.
BUG=b:316421831
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
Make sure that brox device still boots up with this change.
Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81789
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 9bdc197..3d87bf25 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -115,7 +115,7 @@
/* b/316421831: GPP_B16/17 need to be enabled when ISH is enabled later on */
/* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> ISH_I2C_EC_SDA (NC) */
PAD_NC(GPP_B16, NONE),
- /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> NOTE_BOOK_MODE (NC initially) */
+ /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> ISH_I2C_EC_SCL (NC) */
PAD_NC(GPP_B17, NONE),
/* GPP_B18 : GPP_B18 ==> GPP_B18_STRAP */
PAD_NC(GPP_B18, NONE),
@@ -198,7 +198,7 @@
PAD_NC(GPP_E7, NONE),
/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
- /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> SOC_GPP_E9 (NC) */
+ /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */
PAD_NC(GPP_E9, NONE),
/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
PAD_CFG_GPI(GPP_E10, NONE, PLTRST),
diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c
index d8fd44d..512d27e 100644
--- a/src/mainboard/google/brox/variants/brox/fw_config.c
+++ b/src/mainboard/google/brox/variants/brox/fw_config.c
@@ -9,22 +9,24 @@
#define ISH_FIRMWARE_NAME "brox_ish.bin"
static const struct pad_config ish_enable_pads[] = {
+ /* GPP_A16 : ISH_GP5, TABLET_MODE_ODL */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4),
/* GPP_B5 : ISH I2C0_SDA */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
/* GPP_B6 : ISH_I2C0_SCL */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
- /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */
- PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
- /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */
- PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+ /* GPP_B15 : ISH_GP7, LID_OPEN_1V8 */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF5),
/* GPP_D2 : ISH_GP2, SOC_ISH_ACCEL_INT_L */
PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
/* GPP_D3 : ISH_GP3, SOC_ISH_IMU_INT_L */
PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
- /* GPP_B15 : ISH_GP7, LID_OPEN_1V8 */
- PAD_CFG_NF(GPP_B15, NONE, DEEP, NF5),
- /* GPP_A16 : ISH_GP5, TABLET_MODE_ODL */
- PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4),
+ /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+ /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */
+ PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2),
};
static void fw_config_handle(void *unused)