commit 81a69665dc26dde5f8d283ed9944cb8cb5659b9c
author Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Thu Nov 18 12:44:42 2021 +0800
committer Felix Held <felix-coreboot@felixheld.de> Fri Nov 26 11:23:01 2021 +0000
tree 4f9fa78ba5c460ef34bf4f4a20bb20c97284cec1
parent 47516553fb0e2ea9a0606763cf3ade3a76aed2b8

mb/google/corsola: Get RAM code from ADC

On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Corsola the RAM code can be
read from ADC channel 2 and 3.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/mainboard/google/corsola/Makefile.inc

diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc
index 7995f8a..1a9a1c28 100644
--- a/src/mainboard/google/corsola/Makefile.inc
+++ b/src/mainboard/google/corsola/Makefile.inc
@@ -7,11 +7,13 @@
 verstage-y += reset.c
 
 romstage-y += memlayout.ld
+romstage-y += boardid.c
 romstage-y += chromeos.c
 romstage-y += regulator.c
 romstage-y += romstage.c
 
 ramstage-y += memlayout.ld
+ramstage-y += boardid.c
 ramstage-y += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += regulator.c

src/mainboard/google/corsola/boardid.c

diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c
new file mode 100644
index 0000000..285b065
--- /dev/null
+++ b/src/mainboard/google/corsola/boardid.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <soc/auxadc.h>
+
+/* board_id is provided by ec/google/chromeec/ec_boardid.c */
+
+#define ADC_LEVELS 12
+
+enum {
+	/* RAM IDs */
+	RAM_ID_LOW_CHANNEL = 2,
+	RAM_ID_HIGH_CHANNEL = 3,
+};
+
+static const unsigned int ram_voltages[ADC_LEVELS] = {
+	/* ID : Voltage (unit: uV) */
+	[0]  =   74300,
+	[1]  =  211700,
+	[2]  =  318800,
+	[3]  =  428600,
+	[4]  =  541700,
+	[5]  =  665800,
+	[6]  =  781400,
+	[7]  =  900000,
+	[8]  = 1023100,
+	[9]  = 1137000,
+	[10] = 1240000,
+	[11] = 1342600,
+};
+
+static const unsigned int *adc_voltages[] = {
+	[RAM_ID_LOW_CHANNEL] = ram_voltages,
+	[RAM_ID_HIGH_CHANNEL] = ram_voltages,
+};
+
+static uint32_t get_adc_index(unsigned int channel)
+{
+	unsigned int value = auxadc_get_voltage_uv(channel);
+
+	assert(channel < ARRAY_SIZE(adc_voltages));
+	const unsigned int *voltages = adc_voltages[channel];
+	assert(voltages);
+
+	/* Find the closest voltage */
+	uint32_t id;
+	for (id = 0; id < ADC_LEVELS - 1; id++)
+		if (value < (voltages[id] + voltages[id + 1]) / 2)
+			break;
+
+	printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id);
+	return id;
+}
+
+uint32_t ram_code(void)
+{
+	static uint32_t cached_ram_code = BOARD_ID_INIT;
+
+	if (cached_ram_code == BOARD_ID_INIT) {
+		cached_ram_code = (get_adc_index(RAM_ID_HIGH_CHANNEL) << 4 |
+				   get_adc_index(RAM_ID_LOW_CHANNEL));
+		printk(BIOS_DEBUG, "RAM Code: %#02x\n", cached_ram_code);
+	}
+
+	return cached_ram_code;
+}