diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 7c1a52e..2d2879f6 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -101,7 +101,7 @@
 
 static inline bool cpu_is_amd(void)
 {
-	return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON);
+	return CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON);
 }
 
 static inline bool cpu_is_intel(void)
diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
index db8989d..0369ebd 100644
--- a/src/cpu/amd/Kconfig
+++ b/src/cpu/amd/Kconfig
@@ -1,2 +1 @@
-source "src/cpu/amd/agesa/Kconfig"
 source "src/cpu/amd/pi/Kconfig"
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index 5c07a66..94089bd 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -1,2 +1 @@
-subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
 subdirs-$(CONFIG_CPU_AMD_PI) += pi
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
deleted file mode 100644
index d46d2ed..0000000
--- a/src/cpu/amd/agesa/Kconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config CPU_AMD_AGESA
-	bool
-	default n
-	select ARCH_X86
-	select DRIVERS_AMD_PI
-	select TSC_SYNC_LFENCE
-	select UDELAY_LAPIC
-	select LAPIC_MONOTONIC_TIMER
-	select SPI_FLASH if HAVE_ACPI_RESUME
-	select SSE2
-	select CACHE_MRC_SETTINGS
-
-if CPU_AMD_AGESA
-
-config UDELAY_LAPIC_FIXED_FSB
-	int
-	default 200
-
-# TODO: Sync these with definitions in AGESA vendorcode.
-# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
-# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
-
-config DCACHE_RAM_BASE
-	hex
-	default 0x30000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x10000
-
-config DCACHE_BSP_STACK_SIZE
-	hex
-	default 0x4000
-
-config ENABLE_MRC_CACHE
-	bool "Use cached memory configuration"
-	default n
-	select SPI_FLASH
-	help
-	  Try to restore memory training results
-	  from non-volatile memory.
-
-endif # CPU_AMD_AGESA
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
deleted file mode 100644
index 4cacc51..0000000
--- a/src/cpu/amd/agesa/Makefile.inc
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
-postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
-ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc
deleted file mode 100644
index 97a6694..0000000
--- a/src/cpu/amd/smm/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-
-ramstage-y += smm_init.c
diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c
deleted file mode 100644
index 75dd4506..0000000
--- a/src/cpu/amd/smm/smm_init.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
-#include <cpu/x86/smi_deprecated.h>
-#include <string.h>
-
-void smm_init(void)
-{
-	msr_t msr, syscfg_orig, mtrr_aseg_orig;
-
-	/* Back up MSRs for later restore */
-	syscfg_orig = rdmsr(SYSCFG_MSR);
-	mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000);
-
-	/* MTRR changes don't like an enabled cache */
-	disable_cache();
-
-	msr = syscfg_orig;
-
-	/* Allow changes to MTRR extended attributes */
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	/* turn the extended attributes off until we fix
-	 * them so A0000 is routed to memory
-	 */
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	/* set DRAM access to 0xa0000 */
-	msr.lo = 0x18181818;
-	msr.hi = 0x18181818;
-	wrmsr(MTRR_FIX_16K_A0000, msr);
-
-	/* enable the extended features */
-	msr = syscfg_orig;
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	enable_cache();
-	/* copy the real SMM handler */
-	memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start);
-	wbinvd();
-	disable_cache();
-
-	/* Restore SYSCFG and MTRR */
-	wrmsr(SYSCFG_MSR, syscfg_orig);
-	wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig);
-	enable_cache();
-
-	/* CPU MSR are set in CPU init */
-}
-
-void smm_init_completion(void)
-{
-}
diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc
index 6d80c4c..fbbf044 100644
--- a/src/drivers/amd/agesa/Makefile.inc
+++ b/src/drivers/amd/agesa/Makefile.inc
@@ -21,7 +21,4 @@
 ramstage-y += heapmanager.c
 ramstage-y += acpi_tables.c
 
-romstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c
-ramstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c s3_mtrr.c
-
 endif
diff --git a/src/drivers/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c
index 1c09d3f..c4a4e18 100644
--- a/src/drivers/amd/agesa/acpi_tables.c
+++ b/src/drivers/amd/agesa/acpi_tables.c
@@ -8,8 +8,7 @@
 /* Fields were removed from the structure and we cannot add them back
  * without new builds of the binaryPI blobs.
  */
-#if !CONFIG(CPU_AMD_AGESA_BINARY_PI) || \
-	CONFIG(NORTHBRIDGE_AMD_PI_00730F01)
+#if CONFIG(NORTHBRIDGE_AMD_PI_00730F01)
 
 #define HAS_ACPI_SRAT	TRUE
 #define HAS_ACPI_SLIT	TRUE
diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c
index 2ff4d44..b819dff 100644
--- a/src/drivers/amd/agesa/state_machine.c
+++ b/src/drivers/amd/agesa/state_machine.c
@@ -14,10 +14,6 @@
 
 #include <AMD.h>
 
-#if CONFIG(CPU_AMD_AGESA_OPENSOURCE)
-#include "Dispatcher.h"
-#endif
-
 #if ENV_RAMINIT
 #include <PlatformMemoryConfiguration.h>
 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END};
@@ -25,7 +21,6 @@
 
 static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader)
 {
-#if CONFIG(CPU_AMD_AGESA_BINARY_PI)
 	const char ModuleIdentifier[] = AGESA_ID;
 	const void *agesa, *image;
 	size_t file_size;
@@ -37,7 +32,6 @@
 	image = LibAmdLocateImage(agesa, agesa + file_size, 4096,
 		ModuleIdentifier);
 	StdHeader->ImageBasePtr = (void *)image;
-#endif
 }
 
 void agesa_set_interface(struct sysinfo *cb)
@@ -46,15 +40,13 @@
 
 	cb->StdHeader.CalloutPtr = GetBiosCallout;
 
-	if (CONFIG(CPU_AMD_AGESA_BINARY_PI)) {
-		agesa_locate_image(&cb->StdHeader);
-		AMD_IMAGE_HEADER *image =
-			(void *)(uintptr_t)cb->StdHeader.ImageBasePtr;
-		ASSERT(image);
-		AMD_MODULE_HEADER *module =
-			(void *)(uintptr_t)image->ModuleInfoOffset;
-		ASSERT(module && module->ModuleDispatcher);
-	}
+	agesa_locate_image(&cb->StdHeader);
+	AMD_IMAGE_HEADER *image =
+		(void *)(uintptr_t)cb->StdHeader.ImageBasePtr;
+	ASSERT(image);
+	AMD_MODULE_HEADER *module =
+		(void *)(uintptr_t)image->ModuleInfoOffset;
+	ASSERT(module && module->ModuleDispatcher);
 }
 
 AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func,
@@ -62,14 +54,9 @@
 {
 	MODULE_ENTRY dispatcher;
 
-#if CONFIG(CPU_AMD_AGESA_OPENSOURCE)
-	dispatcher = AmdAgesaDispatcher;
-#endif
-#if CONFIG(CPU_AMD_AGESA_BINARY_PI)
 	AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr;
 	AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset;
 	dispatcher = module->ModuleDispatcher;
-#endif
 
 	StdHeader->Func = func;
 	return dispatcher(StdHeader);
diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index 6f6e3d63..2ccfbbf 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -2,7 +2,6 @@
 
 config NORTHBRIDGE_AMD_AGESA
 	bool
-	default CPU_AMD_AGESA
 
 if NORTHBRIDGE_AMD_AGESA
 
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig
index 2378616..b095916 100644
--- a/src/vendorcode/amd/Kconfig
+++ b/src/vendorcode/amd/Kconfig
@@ -1,42 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-if CPU_AMD_AGESA || CPU_AMD_PI || SOC_AMD_PI
+if CPU_AMD_PI || SOC_AMD_PI
 
 menu "AMD Platform Initialization"
 
-choice
-	prompt "AGESA source"
-	default CPU_AMD_AGESA_BINARY_PI if CPU_AMD_PI
-	default CPU_AMD_AGESA_BINARY_PI if SOC_AMD_PI
-	default CPU_AMD_AGESA_OPENSOURCE if CPU_AMD_AGESA
-	help
-	  Select the method for including the AMD Platform Initialization
-	  code into coreboot.  Platform Initialization code is required for
-	  all AMD processors.
-
-config CPU_AMD_AGESA_BINARY_PI
-	bool "binary PI"
-	help
-	  Use a binary PI package.  Generally, these will be stored in the
-	  "3rdparty/blobs" directory.  For some processors, these must be obtained
-	  directly from AMD Embedded Processors Group
-	  (http://www.amd.com/embedded).
-
-config CPU_AMD_AGESA_OPENSOURCE
-	bool "open-source AGESA"
-	help
-	  Build the PI package ("AGESA") from source code in the "vendorcode"
-	  directory.
-
-endchoice
-
-if CPU_AMD_AGESA_OPENSOURCE
-source "src/vendorcode/amd/agesa/Kconfig"
-endif
-
-if CPU_AMD_AGESA_BINARY_PI
 source "src/vendorcode/amd/pi/Kconfig"
-endif
 
 config AGESA_EXTRA_TIMESTAMPS
 	bool "Add instrumentation for AGESA calls"
diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc
index 71898a3..96c3ea9 100644
--- a/src/vendorcode/amd/pi/00670F00/Makefile.inc
+++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc
@@ -85,7 +85,7 @@
 
 agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS])
 
-classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa
+classes-y += libagesa
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
 $(eval $(call create_class_compiler,libagesa,x86_32))
@@ -136,7 +136,7 @@
 
 $(AGESA_POST_MEM_ELF_RMOD): $(AGESA_POST_MEM_ELF)
 
-cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)
+cbfs-files-y += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)
 $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-file := $(CONFIG_AGESA_PRE_MEMORY_BINARY_PI_FILE)
 $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-type := stage
 $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-options :=  --xip
@@ -144,7 +144,7 @@
 # 64 byte alignment.
 $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-align := 4096
 
-cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)
+cbfs-files-y += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)
 $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(AGESA_POST_MEM_ELF_RMOD)
 $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage
 $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-compression := $(CBFS_COMPRESS_FLAG)
@@ -158,7 +158,7 @@
 files_added:: warn_no_agesa
 else
 
-cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME)
+cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME)
 $(CONFIG_AGESA_CBFS_NAME)-file := $(AGESA_BINARYPI_INPUT_FILE)
 
 ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y)
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 9b4659e..d36671a 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -108,7 +108,7 @@
 agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c)
 endif
 
-classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa
+classes-y += libagesa
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
 $(eval $(call create_class_compiler,libagesa,x86_32))
@@ -135,7 +135,7 @@
 
 #######################################################################
 
-cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME)
+cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME)
 $(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE)
 $(CONFIG_AGESA_CBFS_NAME)-type := raw
 $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION)