pci1x2x: remove latency/bridge control/cacheline size settings
Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb
index a132604..f89d1cd 100644
--- a/src/mainboard/nokia/ip530/devicetree.cb
+++ b/src/mainboard/nokia/ip530/devicetree.cb
@@ -33,8 +33,6 @@
device pci 00.0 on
subsystemid 0x13b8 0x0000
end
- register "cltr" = "0x40"
- register "bcr" = "0x7c0"
register "scr" = "0x08449060"
register "mrr" = "0x00007522"
end
diff --git a/src/southbridge/ti/pci1x2x/chip.h b/src/southbridge/ti/pci1x2x/chip.h
index b40194e..4c36761 100644
--- a/src/southbridge/ti/pci1x2x/chip.h
+++ b/src/southbridge/ti/pci1x2x/chip.h
@@ -6,8 +6,5 @@
struct southbridge_ti_pci1x2x_config {
int scr;
int mrr;
- int clsr;
- int cltr;
- int bcr;
};
#endif
diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c
index dfb183c..e59be4f 100644
--- a/src/southbridge/ti/pci1x2x/pci1x2x.c
+++ b/src/southbridge/ti/pci1x2x/pci1x2x.c
@@ -34,12 +34,6 @@
struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
if (conf) {
- /* Cache Line Size (offset 0x0C) */
- pci_write_config8(dev, 0x0C, conf->clsr);
- /* CardBus latency timer (offset 0x1B) */
- pci_write_config8(dev, 0x1B, conf->cltr);
- /* Bridge control (offset 0x3E) */
- pci_write_config16(dev, 0x3E, conf->bcr);
/* System control (offset 0x80) */
pci_write_config32(dev, 0x80, conf->scr);
/* Multifunction routing */