soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handling
After calling FSP MemoryInit API, if there is an error, some FSPs
(such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB.
Check existence of such a HOB and handle it accordingly.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I612393ffac90815606f3f2544bc1518f6912e605
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71952
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h
index a2adfed..10d334f 100644
--- a/src/soc/intel/xeon_sp/include/soc/romstage.h
+++ b/src/soc/intel/xeon_sp/include/soc/romstage.h
@@ -10,5 +10,6 @@
void mainboard_rtc_failed(void);
void save_dimm_info(void);
void mainboard_ewl_check(void);
+void fsp_check_for_error(void);
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c
index d001d61..530e6ea 100644
--- a/src/soc/intel/xeon_sp/romstage.c
+++ b/src/soc/intel/xeon_sp/romstage.c
@@ -17,6 +17,9 @@
printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n");
mainboard_ewl_check();
+ if (CONFIG(ENABLE_FSP_ERROR_INFO))
+ fsp_check_for_error();
+
unlock_pam_regions();
save_dimm_info();