src/soc: Fix typo
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 74151e8..1b1c135 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -469,7 +469,7 @@
/* i2s source clock: gpll
i2s0_outclk_sel: clk_i2s
- i2s0_clk_sel: divider ouput from fraction
+ i2s0_clk_sel: divider output from fraction
i2s0_pll_div_con: 0*/
write32(&cru_ptr->cru_clksel_con[4],
RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0,
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 5422deb..0b8c83f 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -804,7 +804,7 @@
int v;
/**
- * clk_i2s0_sel: divider ouput from fraction
+ * clk_i2s0_sel: divider output from fraction
* clk_i2s0_pll_sel source clock: cpll
* clk_i2s0_div_con: 1 (div+1)
*/