src/soc: Fix typo
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 4704d1c..2dc8c2c 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -156,7 +156,7 @@
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
- /* PCIe ouput clocks type to Pcie devices.
+ /* PCIe output clocks type to Pcie devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index a6e03ca..a147d92 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -116,7 +116,7 @@
/* Estimated maximum platform power in Watts */
u16 psys_pmax;
- /* Wether to ignore VT-d support of the SKU */
+ /* Whether to ignore VT-d support of the SKU */
int ignore_vtd;
/*
diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h
index 6994ca2..d9ab67b 100644
--- a/src/soc/nvidia/tegra124/chip.h
+++ b/src/soc/nvidia/tegra124/chip.h
@@ -88,7 +88,7 @@
int pixel_clock;
- /* The minimum link configuraton settings */
+ /* The minimum link configuration settings */
u32 lane_count;
u32 enhanced_framing;
u32 link_bw;
diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c
index d5019d9..536ad31 100644
--- a/src/soc/nvidia/tegra124/sdram_lp0.c
+++ b/src/soc/nvidia/tegra124/sdram_lp0.c
@@ -23,7 +23,7 @@
#include <stdlib.h>
/*
- * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from
+ * This function reads SDRAM parameters (and a few CLK_RST register values) from
* the common BCT format and writes them into PMC scratch registers (where the
* BootROM expects them on LP0 resume). Since those store the same values in a
* different format, we follow a "translation table" taken from Nvidia's U-Boot
diff --git a/src/soc/nvidia/tegra210/chip.h b/src/soc/nvidia/tegra210/chip.h
index 6a2aa84..75d2497 100644
--- a/src/soc/nvidia/tegra210/chip.h
+++ b/src/soc/nvidia/tegra210/chip.h
@@ -76,7 +76,7 @@
int hpd_plug_min_us;
int hpd_irq_min_us;
- /* The minimum link configuraton settings */
+ /* The minimum link configuration settings */
u32 lane_count;
u32 enhanced_framing;
u32 link_bw;
diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c
index 8d4a225..3af7958 100644
--- a/src/soc/qualcomm/ipq806x/uart.c
+++ b/src/soc/qualcomm/ipq806x/uart.c
@@ -329,7 +329,7 @@
GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S);
write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE);
- /* Intialize UART_DM */
+ /* Initialize UART_DM */
msm_boot_uart_dm_init(dm_base);
}
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 74151e8..1b1c135 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -469,7 +469,7 @@
/* i2s source clock: gpll
i2s0_outclk_sel: clk_i2s
- i2s0_clk_sel: divider ouput from fraction
+ i2s0_clk_sel: divider output from fraction
i2s0_pll_div_con: 0*/
write32(&cru_ptr->cru_clksel_con[4],
RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0,
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 5422deb..0b8c83f 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -804,7 +804,7 @@
int v;
/**
- * clk_i2s0_sel: divider ouput from fraction
+ * clk_i2s0_sel: divider output from fraction
* clk_i2s0_pll_sel source clock: cpll
* clk_i2s0_div_con: 1 (div+1)
*/