tree fc95c18643f50581696e987b7add3bec53f59365
parent f25f0954c38f12603f083e89653265e8d4d60501
author Arthur Heymans <arthur@aheymans.xyz> 1619788252 +0200
committer Felix Held <felix-coreboot@felixheld.de> 1620137046 +0000

drivers/intel/fsp1_1: Remove verstage compilation units

Only SOC_INTEL_BRASWELL is using FSP1.1. It has too little CAR
available set up by FSP-T to have VBOOT_STARTS_IN_BOOTBLOCK and
therefore verstage is not possible either.

Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>