0x00000000, 0x100000000, WB, # RAM
# Above entry is needed because below 4G allocated memory range is
# only known after FSP memory init completes. However, FSP migrates to memory
# from cache as RAM before it exits FSP Memory Init. Hence we need to add
# page table entries for this entire range before FSP Memory Init. The
# overlapped MMIO ranges will be overridden by below entries.
0xd0000000, 0x100000000, UC, NX # All of MMIO
# Maximum 16MiB of mmio SPI flash decode.
0xff000000, 0x100000000, WP, # memory-mapped SPI
# MMIO XIP bootblock C_ENV_BOOTBLOCK_SIZE
0xffff8000, 0x100000000, WP, # XIP bootblock
# DCACHE_RAM_BASE + DCACHE_RAM_SIZE
0xfef00000, 0xff000000, WB, NX # CAR
# VERSTAGE_ADDR ~63KiB
0xfef40000, 0xfefc0000, WB, # verstage
# ROMSTAGE_ADDR ~68KiB
0xfef20000, 0xfefc0000, WB, # romstage
# FSP_M_ADDR  ~408 KiB (non-debug)
0xfef40000, 0xfefc0000, WB, # fsp-m