baytrail: Add reserved MMIO regions to ACPI
Add a length define for all the reserved MMIO regions and
use them in the ACPI code to reserve the regions there.
Add a region for the "abort page" documented in the EDS.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175624
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4934
Tested-by: build bot (Jenkins)
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 307841b..81bcd32 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -30,3 +30,32 @@
TRP0, 8 // IO-Trap at 0x808
}
}
+
+/* Device Resource Consumption */
+Device (PDRC)
+{
+ Name (_HID, EISAID("PNP0C02"))
+ Name (_UID, 1)
+
+ Name (PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+ Memory32Fixed(ReadWrite, IO_BASE_ADDRESS, IO_BASE_SIZE)
+ Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+ Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+#if CONFIG_CHROMEOS_RAMOOPS
+ Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+ CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
+#endif
+ })
+
+ // Current Resource Settings
+ Method (_CRS, 0, Serialized)
+ {
+ Return(PDRS)
+ }
+}
diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/baytrail/iomap.h
index d46a0fe..77a55f5 100644
--- a/src/soc/intel/baytrail/baytrail/iomap.h
+++ b/src/soc/intel/baytrail/baytrail/iomap.h
@@ -21,21 +21,62 @@
#define _BAYTRAIL_IOMAP_H_
-/* Memory Mapped IO bases. */
+/*
+ * Memory Mapped IO bases.
+ */
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+#define MCFG_BASE_SIZE 0x10000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS 0xfeb00000
+#define ABORT_BASE_SIZE 0x00100000
+
+/* Power Management Controller */
#define PMC_BASE_ADDRESS 0xfed03000
+#define PMC_BASE_SIZE 0x400
+
+/* IO Memory */
#define IO_BASE_ADDRESS 0xfed0c000
+#define IO_BASE_SIZE 0x4000
+
+/* Intel Legacy Block */
#define ILB_BASE_ADDRESS 0xfed08000
+#define ILB_BASE_SIZE 0x400
+
+/* SPI Bus */
#define SPI_BASE_ADDRESS 0xfed01000
+#define SPI_BASE_SIZE 0x400
+
+/* MODPHY */
#define MPHY_BASE_ADDRESS 0xfef00000
+#define MPHY_BASE_SIZE 0x100000
+
+/* Power Management Unit */
#define PUNIT_BASE_ADDRESS 0xfed05000
+#define PUNIT_BASE_SIZE 0x800
+
+/* Root Complex Base Address */
#define RCBA_BASE_ADDRESS 0xfed1c000
+#define RCBA_BASE_SIZE 0x400
+
+/* High Performance Event Timer */
#define HPET_BASE_ADDRESS 0xfed00000
+#define HPET_BASE_SIZE 0x400
+
+/* Temporary Base Address */
#define TEMP_BASE_ADDRESS 0xfd000000
-/* IO Port base */
+/*
+ * IO Port bases.
+ */
#define ACPI_BASE_ADDRESS 0x0400
+#define ACPI_BASE_SIZE 0x80
+
#define GPIO_BASE_ADDRESS 0x0500
+#define GPIO_BASE_SIZE 0x100
+
#define SMBUS_BASE_ADDRESS 0xefa0
#endif /* _BAYTRAIL_IOMAP_H_ */
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index c71ab7e..f8b4f18 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -41,13 +41,14 @@
static void sc_add_mmio_resources(device_t dev)
{
- add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, 1024);
- add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, 16 * 1024);
- add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, 1024);
- add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, 1024);
- add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, 1024 * 1024);
- add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, 2048);
- add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, 1024);
+ add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
+ add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
+ add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
+ add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
+ add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
+ add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
+ add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
+ add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
}
/* Default IO range claimed by the LPC device. The upper bound is exclusive. */