mb/intel/mtlrvp: Add configuration for UART devices
This patch adds below configuration for MTL-RVP UART devices,
Interface -> UART0
PCI -> 0:0x1e:0
Device -> AP UART
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp ito chromeOS
using subsequent patches in the train. UART logs appear on AP console.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index a571bb5..349e9de 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -22,6 +22,10 @@
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select HAS_RECOVERY_MRC_CACHE
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select INTEL_LPSS_UART_FOR_CONSOLE
+
config MAINBOARD_DIR
default "intel/mtlrvp"
@@ -81,4 +85,8 @@
config VBOOT
select VBOOT_LID_SWITCH
+config UART_FOR_CONSOLE
+ int
+ default 0
+
endif # BOARD_INTEL_MTLRVP_COMMON
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 10b4cea..d28b7b1 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -11,6 +11,12 @@
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
+ register "serial_io_uart_mode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
device domain 0 on
device ref igpu on end
device ref heci1 on end